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features ? 80c52x2 core (6 clocks per instruction) ? maximum core frequency 48 mhz in x1 mode, 24 mhz i n x2 mode ? dual data pointer ? full-duplex enhanced uart (euart), txd and rxd are 5 volt tolerant ? three 16-bit timer/counters: t0, t1 and t2 ? 256 bytes of scratchpad ram ? 8/16/32-kbyte on-chip rom ? 512 byte or 32-kbyte eeprom (1) ? on-chip expanded ram (eram): 1024 bytes ? integrated power monitor (por/pfd) to supervise int ernal power supply ? usb 2.0 full speed compliant module with interrupt on transfer completion (12mbps) ? endpoint 0 for control transfers: 32-byte fifo ? 6 programmable endpoints with in or out directions and with bulk, interrupt or isochronous transfers ? endpoint 1, 2, 3: 32-byte fifo ? endpoint 4, 5: 2 x 64-byte fifo with double buffer ing (ping-pong mode) ? suspend/resume interrupts ? power-on reset and usb bus reset ? 48 mhz dpll for full-speed bus operation ? usb bus disconnection on microcontroller request ? 5 channels programmable counter array (pca) with 16 -bit counter, high-speed output, compare/capture, pwm and watchdog timer cap abilities ? programmable hardware watchdog timer (one-time enab led with reset-out): 50 ms to 6s at 4 mhz ? keyboard interrupt interface on port p1 (8 bits) ? twi (two wire interface) 400kbit/s ? spi interface (master/slave mode) miso,mosi,sck and ss are 5 volt tolerant ? 34 i/o pins ? 4 direct-drive led outputs with programmable curren t sources: 2-6-10 ma typical ? 4-level priority interrupt system (11 sources) ? idle and power-down modes ? 0 to 32 mhz on-chip oscillator with analog pll for 48 mhz synthesis ? industrial temperature range ? low voltage range supply: 2.7v to 3.6v ? packages: die so28, qfn32, mlf48, tqfp64 notes: 1. eeprom only available on mlf48 1. description at83c5134/35/36 are high performance rom versions of the 80c51 single-chip 8-bit microcontrollers wit h full speed usb functions. at83c5134/35 is pin compatible with at89c5130a 16- kbytes in-system programmable flash microcontroller s. 8-bit microcontroller with full speed usb device at83c5134 at83c5135 at83c5136
2 7683c?usb?11/07 at83c5134/35/36 this allows to use at89c5130a for development, pre- production and flexibility, while using at83c5134/35 for cost reduction in mass production. similarly at83c5136 is pin compatible with at89c5131a 32-kbytes flash microcontroller. at83c5134/35/36 features a full-speed usb module co mpatible with the usb specifications version 2.0. this module integrates the usb transce ivers and the serial interface engine (sie) with digital phase locked loop and 48 mhz clock rec overy. usb event detection logic (reset and suspend/resume) and fifo buffers supporting the mandatory control endpoint (ep0) and 5 versatile endpoints (ep1/ep2/ep3/ep4/ep5) with mi nimum software overhead are also part of the usb module. at83c5134/35/36 retains the features of the atmel 80c52 with extend ed rom cpacity (8/16/32 kbytes), 256 bytes of internal ram, a 4-level inter rupt system, two 16-bit timer/counters (t0/t1), a full duplex enhanced uart (euart) and an on-chip oscillator. in addition, at83c5134/35/36 has an on-chip expande d ram of 1024 bytes (eram), a dual- data pointer, a 16-bit up/down timer (t2), a progra mmable counter array (pca), up to 4 pro- grammable led current sources, a programmable hardw are watchdog and a power-on reset. at83c5134/35/36 has two software-selectable modes o f reduced activity for further reduction in power consumption. in the idle mode the cpu is froz en while the timers, the serial ports and the interrupt system are still operating. in the power- down mode the ram is saved, the peripheral clock is frozen, but the device has full wake-up ca pability through usb events or external interrupts.
3 7683c?usb?11/07 at83c5134/35/36 3. block diagram * eeprom only available in mlf48 notes: 1. alternate function of port 1 2. alternate function of port 3 3. alternate function of port 4 timer 0 int ram 256x8 t0 t1 rxd txd wr rd ea psen ale xtal2 xtal1 euart cpu timer 1 int1 ctrl int0 (2) (2) c51 core (2) (2) (2) (2) port 0 p0 port 1 port 2 port 3 parallel i/o ports & ext. bus p1 p2 p3 eram 1kx8 pca rst watch dog cex eci vss vdd (2) (2) (1) (1) timer2 t2ex t2 (1) (1) port 4 p4 32kx8 rom + brg usb d - d + key board kin eeprom* 1kx8 spi miso mosi sck (1) (1) (1) ss (1) twi scl sda twi interface
4 7683c?usb?11/07 at83c5134/35/36 4. pinout description 4.1 pinout figure 4-1. at83c5134/35/36 64-pin vqfp pinout p3.4/t0 p3.5/t1/led1 ale ea psen pllf vref d- d+ nc nc nc nc 17 18 22 21 20 19 25 24 23 26 27 62 61 60 59 58 63 57 56 55 54 53 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 44 43 42 41 40 39 38 vqfp64 64 52 12 13 28 29 36 37 51 50 49 35 33 34 14 15 16 30 31 32 p1.1/t2ex/kin1/ss p1.7/cex4/kin7/mosi p1.3/cex0/kin3 p1.5/cex2/kin5/miso p1.6/cex3/kin6/sck p2.7/a15 p2.6/a14 p4.1/sda p1.2/eci/kin2 p1.4/cex1/kin4 p1.0/t2/kin0 nc xtal2 rst p3.7/rd /led3 p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 nc nc p3.0/rxd nc p0.0/ad0 avss p3.2/int0 p3.6/wr /led2 p3.1/txd p3.3/int1 /led0 vss nc p0.6/ad6 p0.7/ad7 p2.5/a13 p0.3/ad3 p0.5/ad5 p0.4/ad4 p0.2/ad2 p0.1/ad1 p4.0/scl xtal1 avdd nc nc nc nc nc nc nc vdd
5 7683c?usb?11/07 at83c5134/35/36 figure 4-2. at83c5134/35/36 48-pin mlf pinout figure 4-3. at83c5134/35/36 28-pin so pinout 5 4 3 2 1 6 48 8 9 10 11 12 13 14 15 16 17 18 46 45 44 43 42 41 40 39 38 37 36 mlf48 7 47 19 20 32 33 34 35 p1.1/t2ex/kin1/ss p1.0/t2/kin0 p0.6/ad6 ale p0.7/ad7 ea psen p1.7/cex4/kin7/mosi p1.3/cex0/kin3 p1.5/cex2/kin5/miso p1.6/cex3/kin6/sck pllf p3.0/rxd avss p2.6/a14 xtal1 p2.5/a13 p0.3/ad3 p0.5/ad5 p0.4/ad4 vref p0.2/ad2 p0.0/ad0 p0.1/ad1 avdd p3.2/int0 p3.6/wr /led2 xtal2 rst p3.1/txd p3.3/int1 /led0 p3.7/rd /led3 d- p2.1/a9 p2.2/a10 p2.3/a11 vss p2.4/a12 p4.1/sda d+ p4.0/scl p1.2/eci/kin2 p1.4/cex1/kin4 p3.4/t0 p3.5/t1/led1 vdd p2.7/a15 31 30 29 28 27 26 25 24 23 22 21 p2.0/a8 p1.1/t2ex/kin1/ss pllf p3.0/rxd p1.0/t2/kin0 avss vdd xtal1 xtal2 p3.2/int0 p3.5/t1/led1 p3.6/wr/led2 p3.7/rd/led3 d- p1.4/cex1/kin4 vss d+ p1.2/eci/kin2 p1.3/cex0/kin3 p1.5/cex2/kin5/miso rst p1.6/cex3/kin6/sck p1.7/cex4/kin7/mosi p4.0/scl vref p3.1/txd p3.4/t0 1 2 3 4 5 6 7 8 9 10 11 12 28 27 26 25 24 23 22 21 20 19 18 17 so28 13 14 16 15 p4.1/sda p3.3/int1/led0
6 7683c?usb?11/07 at83c5134/35/36 figure 4-4. at83c5134/35/36 32-pin qfn pinout 4.2 signals all the at83c5134/35/36 signals are detailed by fun ctionality on table 4-1 through table 4-12. table 4-1. keypad interface signal description table 4-2. programmable counter array signal description 1 2 3 4 5 6 qfn32 7 p1.1/t2ex/kin1/ss p1.7/cex4/kin7/mosi p1.3/cex0/kin3 p1.5/cex2/kin5/miso p1.6/cex3/kin6/sck p3.0/rxd avss xtal1 vref avdd p3.2/int0 p3.5/t1/led1 xtal2 rst p3.1/txd p3.3/int1 /led0 p3.7/rd /led3 d- vss p4.1/sda d+ p4.0/scl p1.2/eci/kin2 p1.4/cex1/kin4 p3.4/t0 p1.0/t2/kin0 vdd 8 pllf p3.6/wr /led2 uvss nc vss 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 note : the metal plate can be connected to vss signal name type description alternate function kin[7:0) i keypad input lines holding one of these pins high or low for 24 oscill ator periods triggers a keypad interrupt if enabled. held line is reported in the kbcon register. p1[7:0] signal name type description alternate function eci i external clock input p1.2 cex[4:0] i/o capture external input compare external output p1.3 p1.4 p1.5 p1.6 p1.7
7 7683c?usb?11/07 at83c5134/35/36 table 4-3. serial i/o signal description table 4-5. led signal description signal name type description alternate function rxd i serial input the serial input for extended uart. this i/o is 5 v olt tolerant. p3.0 txd o serial output the serial output for extended uart. this i/o is 5 volt tolerant. p3.1 table 4-4. timer 0, timer 1 and timer 2 signal description signal name type description alternate function int0 i timer 0 gate input int0 serves as external run control for timer 0, when s elected by gate0 bit in tcon register. external interrupt 0 int0 input set ie0 in the tcon register. if bit it0 in this register is set, bits ie0 are set by a falling edge on int0 . if bit it0 is cleared, bits ie0 is set by a low l evel on int0 . p3.2 int1 i timer 1 gate input int1 serves as external run control for timer 1, when s elected by gate1 bit in tcon register. external interrupt 1 int1 input set ie1 in the tcon register. if bit it1 in this register is set, bits ie1 are set by a falling edge on int1 . if bit it1 is cleared, bits ie1 is set by a low l evel on int1 . p3.3 t0 i timer counter 0 external clock input when timer 0 operates as a counter, a falling edge on the t0 pin increments the count. p3.4 t1 i timer/counter 1 external clock input when timer 1 operates as a counter, a falling edge on the t1 pin increments the count. p3.5 t2 i o timer/counter 2 external clock input timer/counter 2 clock output p1.0 t2ex i timer/counter 2 reload/capture/direction contr ol input p1.1 signal name type description alternate function led[3:0] o direct drive led output these pins can be directly connected to the cathode of standard leds without external current limiting resistors. the typical cu rrent of each output can be programmed by software to 2, 6 or 10 ma. several ou tputs can be connected together to get higher drive capabilities. p3.3 p3.5 p3.6 p3.7
8 7683c?usb?11/07 at83c5134/35/36 table 4-6. twi signal description table 4-7. spi signal description table 4-8. ports signal description signal name type description alternate function scl i/o scl: twi serial clock scl output the serial clock to slave peripherals. scl input the serial clock from master. p4.0 sda i/o sda: twi serial data scl is the bidirectional twi data line. p4.1 signal name type description alternate function ss i/o ss : spi slave select . this i/o is 5 volt tolerant p1.1 miso i/o miso: spi master input slave output line when spi is in master mode, miso receives data from the slave peripheral. when spi is in slave mode, miso outputs data to the mast er controller. this i/o is 5 volt tolerant p1.5 sck i/o sck: spi serial clock sck outputs clock to the slave peripheral or receiv e clock from the master. this i/o is 5 volt tolerant. p1.6 mosi i/o mosi: spi master output slave input line when spi is in master mode, mosi outputs data to th e slave peripheral. when spi is in slave mode, mosi receives data from the m aster controller. this i/o is 5 volt tolerant. p1.7 signal name type description alternate function p0[7:0] i/o port 0 p0 is an 8-bit open-drain bidirectional i/o port. p ort 0 pins that have 1s written to them float and can be used as hi gh impedance inputs. to avoid any parasitic current co nsumption, floating p0 inputs must be pulled to v dd or v ss . ad[7:0] p1[7:0] i/o port 1 p1 is an 8-bit bidirectional i/o port with internal pull-ups. kin[7:0] t2 t2ex eci cex[4:0] p2[7:0] i/o port 2 p2 is an 8-bit bidirectional i/o port with internal pull-ups. a[15:8]
9 7683c?usb?11/07 at83c5134/35/36 table 4-9. clock signal description table 4-10. usb signal description table 4-11. system signal description p3[7:0] i/o port 3 p3 is an 8-bit bidirectional i/o port with internal pull-ups. led[3:0] rxd txd int0 int1 t0 t1 wr rd p4[1:0] i/o port 4 p4 is an 2-bit open port. scl sda signal name type description alternate function xtal1 i input to the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, its output is conne cted to this pin. - xtal2 o output of the on-chip inverting oscillator amplifie r to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, leave xtal2 unconne cted. - pllf i pll low pass filter input receives the rc network of the pll low pass filter (see figure 5-1 on page 11 ). - signal name type description alternate function d+ i/o usb data + signal set to high level under reset. - d- i/o usb data - signal set to low level under reset. - vref o usb reference voltage connect this pin to d+ using a 1.5 k resistor to use the detach function. - signal name type description alternate function ad[7:0] i/o multiplexed address/data lsb for external access data lsb for slave port access (used for 8-bit and 16-bit modes) p0[7:0] a[15:8] i/o address bus msb for external access data msb for slave port access (used for 16-bit mod e only) p2[7:0] signal name type description alternate function
10 7683c?usb?11/07 at83c5134/35/36 rd i/o read signal read signal asserted during external data memory re ad operation. control input for slave port read access cycles. p3.7 wr i/o write signal write signal asserted during external data memory w rite operation. control input for slave write access cycles. p3.6 rst i/o reset holding this pin low for 64 oscillator periods whil e the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage lower than v il is applied, whether or not the oscillator is runni ng. this pin has an internal pull-up resistor which all ows the device to be reset by connecting a capacitor between this pin and vss. asserting rst when the chip is in idle mode or power-down mode r eturns the chip to normal operation. this pin is set to 0 for at least 12 oscillator per iods when an internal reset occurs (hardware watchdog or power monitor). - ale o address latch enable output the falling edge of ale strobes the address into ex ternal latch. this signal is active only when reading or writing external memory using movx instructions. - psen o program strobe enable / hardware conditions input f or isp used as input under reset to detect external hardwa re conditions of isp mode - ea i external access enable this pin must be held low to force the device to fe tch code from external program memory starting at address 0000h. it is latched dur ing reset and cannot be dynamically changed during operation. - table 4-12. power signal description signal name type description alternate function avss gnd alternate ground avss is used to supply the on-chip pll and the usb pad. - avdd pwr alternate supply voltage avdd is used to supply the on-chip pll and the usb pad. - vss gnd digital ground vss is used to supply the buffer ring and the digit al core. - vdd pwr digital supply voltage vdd is used to supply the buffer ring on all versio ns of the device. it is also used to power the on-chip voltage regula tor of the standard versions or the digital core of the low power versions. - vref o usb pull-up controlled output vref is used to control the usb d+ 1.5 k pull up. the vref output is in high impedance when the bit d etach is set in the usbcon register. - signal name type description alternate function
11 7683c?usb?11/07 at83c5134/35/36 5. typical application 5.1 recommended external components all the external components described in the figure below must be implemented as close as pos- sible from the microcontroller package. the following figure represents the typical wiring schematic. figure 5-1. typical application vss xtal1 xtal2 q 22pf 22pf vss pllf 560 820pf 150pf vss vss avss vss d- d+ 27r 27r vref 1.5k usb d+ d- vbus gnd vss vdd avdd vdd 4.7f vss 100nf vss 100nf vss at83c5134/35/3
12 7683c?usb?11/07 at83c5134/35/36 5.2 pcb recommandations figure 5-2. usb pads note: no sharp angle in above drawing. figure 5-3. usb pll d+ vref d- usb connector wires must be routed in parallel and components must be if possible, isolate d+ and d- signals from other sig nals with ground wires must be as short as possible close to the microcontroller pllf avss components must be isolate filter components with a ground wire microcontroller close to the c2 c1 r
13 7683c?usb?11/07 at83c5134/35/36 6. clock controller 6.1 introduction the at83c5134/35/36 clock controller is based on an on-chip oscillator feeding an on-chip phase lock loop (pll). all the internal clocks to t he peripherals and cpu core are generated by this controller. the at83c5134/35/36 x1 and x2 pins are the input an d the output of a single-stage on-chip inverter (see figure 6-1) that can be configured wit h off-chip components as a pierce oscillator (see figure 6-2). value of capacitors and crystal ch aracteristics are detailed in the section ?dc characteristics?. the x1 pin can also be used as input for an externa l 48 mhz clock. the clock controller outputs three different clocks as shown in figure 6-1: ? a clock for the cpu core ? a clock for the peripherals which is used to gener ate the timers, pca, wd, and port sampling clocks ? a clock for the usb controller these clocks are enabled or disabled depending on t he power reduction mode as detailed in section ?power management?, page 135. figure 6-1. oscillator block diagram 6.2 oscillator two clock sources are available for cpu: ? crystal oscillator on x1 and x2 pins: up to 32 mhz ? external 48 mhz clock on x1 pin x1 x2 pd pcon.1 idl pcon.0 peripheral cpu core 01 x2 ckcon.0 2 clock clock ext48 pllcon.2 01 pll usb clock
14 7683c?usb?11/07 at83c5134/35/36 in order to optimize the power consumption, the osc illator inverter is inactive when the pll out- put is not selected for the usb device. figure 6-2. crystal connection 6.3 pll 6.3.1 pll description the at83c5134/35/36 pll is used to generate interna l high frequency clock (the usb clock) synchronized with an external low-frequency (the pe ripheral clock). the pll clock is used to generate the usb interface clock. figure 6-3 shows t he internal structure of the pll. the pfld block is the phase frequency comparator an d lock detector. this block makes the comparison between the reference clock coming from the n divider and the reverse clock com- ing from the r divider and generates some pulses on the up or down signal depending on the edge position of the reverse clock. the pllen bit i n pllcon register is used to enable the clock generation. when the pll is locked, the bit p lock in pllcon register (see figure 6-3) is set. the chp block is the charge pump that generates the voltage reference for the vco by inject- ing or extracting charges from the external filter connected on pllf pin (see figure 6-4). value of the filter components are detailed in the sectio n ?dc characteristics?. the vco block is the voltage controlled oscillator controlled by the voltage v ref produced by the charge pump. it generates a square wave signal: the pll clock. figure 6-3. pll block diagram and symbol vss x1 x2 q c1 c2 pllen pllcon.1 n3:0 n divider r divider vco usb clock usbclk osc clk r 1 + ( ) n 1 + ----------------------------------------------- = osc clock pfld plock pllcon.0 pllf chp vref up down r3:0 usb clock usb clock symbol
15 7683c?usb?11/07 at83c5134/35/36 figure 6-4. pll filter connection the typical values are: r = 560 , c1 = 820 pf, c2 = 150 pf. 6.3.2 pll programming the pll is programmed using the flow shown in figur e 6-5. as soon as clock generation is enabled user must wait until the lock indicator is set to ensure the clock output is stable. figure 6-5. pll programming flow 6.3.3 divider values to generate a 48 mhz clock using the pll, the divid er values have to be configured following the oscillator frequency. the typical divider value s are shown in table 6-1 . table 6-1. typical divider values vss pllf r c1 c2 vss pll programming configure dividers n3:0 = xxxxb r3:0 = xxxxb enable pll pllen = 1 pll locked? lock = 1? oscillator frequency r+1 n+1 plldiv 3 mhz 16 1 f0h 6 mhz 8 1 70h 8 mhz 6 1 50h 12 mhz 4 1 30h 16 mhz 3 1 20h 18 mhz 8 3 72h 20 mhz 12 5 b4h 24 mhz 2 1 10h
16 7683c?usb?11/07 at83c5134/35/36 6.4 registers table 6-2. ckcon0 (s:8fh) clock control register 0 reset value = 0000 0000b 32 mhz 3 2 21h 40 mhz 12 10 b9h oscillator frequency r+1 n+1 plldiv 7 6 5 4 3 2 1 0 twix2 wdx2 pcax2 six2 t2x2 t1x2 t0x2 x2 bit number bit mnemonic description 7 twix2 twi clock this control bit is validated when the cpu clock x2 is set. when x2 is low, this bit has no effect. clear to select 6 clock periods per peripheral cloc k cycle. set to select 12 clock periods per peripheral clock cycle. 6 wdx2 watchdog clock this control bit is validated when the cpu clock x2 is set. when x2 is low, this bit has no effect. clear to select 6 clock periods per peripheral cloc k cycle. set to select 12 clock periods per peripheral clock cycle. 5 pcax2 programmable counter array clock this control bit is validated when the cpu clock x2 is set. when x2 is low, this bit has no effect. clear to select 6 clock periods per peripheral cloc k cycle. set to select 12 clock periods per peripheral clock cycle. 4 six2 enhanced uart clock (mode 0 and 2) this control bit is validated when the cpu clock x2 is set. when x2 is low, this bit has no effect. clear to select 6 clock periods per peripheral cloc k cycle. set to select 12 clock periods per peripheral clock cycle. 3 t2x2 timer2 clock this control bit is validated when the cpu clock x2 is set. when x2 is low, this bit has no effect. clear to select 6 clock periods per peripheral cloc k cycle. set to select 12 clock periods per peripheral clock cycle. 2 t1x2 timer1 clock this control bit is validated when the cpu clock x2 is set. when x2 is low, this bit has no effect. clear to select 6 clock periods per peripheral cloc k cycle. set to select 12 clock periods per peripheral clock cycle. 1 t0x2 timer0 clock this control bit is validated when the cpu clock x2 is set. when x2 is low, this bit has no effect. clear to select 6 clock periods per peripheral cloc k cycle. set to select 12 clock periods per peripheral clock cycle. 0 x2 system clock control bit clear to select 12 clock periods per machine cycle (std mode, f cpu = f per = f osc / 2). set to select 6 clock periods per machine cycle (x2 mode, f cpu = f per = f osc ).
17 7683c?usb?11/07 at83c5134/35/36 table 6-3. ckcon1 (s:afh) clock control register 1 reset value = 0000 0000b table 6-4. pllcon (s:a3h) pll control register reset value = 0000 0000b table 6-5. plldiv (s:a4h) pll divider register reset value = 0000 0000 7 6 5 4 3 2 1 0 - - - - - - - spix2 bit number bit mnemonic description 7-1 - reserved the value read from this bit is always 0. do not se t this bit. 0 spix2 spi clock this control bit is validated when the cpu clock x2 is set. when x2 is low, this bit has no effect. clear to select 6 clock periods per peripheral cloc k cycle. set to select 12 clock periods per peripheral clock cycle. 7 6 5 4 3 2 1 0 - - - - - ext48 pllen plock bit number bit mnemonic description 7-3 - reserved the value read from this bit is always 0. do not se t this bit. 2 ext48 external 48 mhz enable bit set this bit to bypass the pll and disable the crys tal oscillator. clear this bit to select the pll output as usb cloc k and to enable the crystal oscillator. 1 pllen pll enable bit set to enable the pll. clear to disable the pll. 0 plock pll lock indicator set by hardware when pll is locked. clear by hardware when pll is unlocked. 7 6 5 4 3 2 1 0 r3 r2 r1 r0 n3 n2 n1 n0 bit number bit mnemonic description 7-4 r3:0 pll r divider bits 3-0 n3:0 pll n divider bits
18 7683c?usb?11/07 at83c5134/35/36 7. sfr mapping the special function registers (sfrs) of the at83c5 134/35/36 fall into the following categories: ? c51 core registers: acc, b, dph, dpl, psw, sp ? i/o port registers: p0, p1, p2, p3, p4 ? timer registers: t2con, t2mod, tcon, th0, th1, th2 , tmod, tl0, tl1, tl2, rcap2l, rcap2h ? serial i/o port registers: saddr, saden, sbuf, sco n ? pca (programmable counter array) registers: ccon, cmod, ccapmx, cl, ch, ccapxh, ccapxl (x: 0 to 4) ? power and clock control registers: pcon ? hardware watchdog timer registers: wdtrst, wdtprg ? interrupt system registers: ien0, ipl0, iph0, ien1 , ipl1, iph1 ? keyboard interface registers: kbe, kbf, kbls ? led register: ledcon ? two wire interface (twi) registers: sscon, sscs, s sdat, ssadr ? serial port interface (spi) registers: spcon, spst a, spdat ? usb registers: uxxx (17 registers) ? pll registers: pllcon, plldiv ? brg (baud rate generator) registers: brl, bdrcon ? others: auxr, auxr1, ckcon0, ckcon1
19 7683c?usb?11/07 at83c5134/35/36 the table below shows all sfrs with their address a nd their reset value. note: 1. fcon access is reserved for the flash api an d isp software. the special function registers (sfrs) of the at89c5 131 fall into the following categories: table 7-1. sfr descriptions bit addressable non-bit addressable 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h uepint 0000 0000 ch 0000 0000 ccap0h xxxx xxxx ccap1h xxxx xxxx ccap2h xxxx xxxx ccap3h xxxx xxxx ccap4h xxxx xxxx ffh f0h b 0000 0000 ledcon 0000 0000 f7h e8h cl 0000 0000 ccap0l xxxx xxxx ccap1l xxxx xxxx ccap2l xxxx xxxx ccap3l xxxx xxxx ccap4l xxxx xxxx efh e0h acc 0000 0000 ubyctlx 0000 0000 ubycthx 0000 0000 e7h d8h ccon 00x0 0000 cmod 00xx x000 ccapm0 x000 0000 ccapm1 x000 0000 ccapm2 x000 0000 ccapm3 x000 0000 ccapm4 x000 0000 dfh d0h psw 0000 0000 uepconx 1000 0000 ueprst 0000 0000 d7h c8h t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 uepstax 0000 0000 uepdatx 0000 0000 cfh c0h p4 xxxx 1111 uepien 0000 0000 spcon 0001 0100 spsta 0000 0000 spdat xxxx xxxx usbaddr 1000 0000 uepnum 0000 0000 c7h b8h ipl0 x000 000 saden 0000 0000 ufnuml 0000 0000 ufnumh 0000 0000 usbcon 0000 0000 usbint 0000 0000 usbien 0000 0000 bfh b0h p3 1111 1111 ien1 x0xx x000 ipl1 x0xx x000 iph1 x0xx x000 iph0 x000 0000 b7h a8h ien0 0000 0000 saddr 0000 0000 ckcon1 0000 0000 afh a0h p2 1111 1111 auxr1 xxxx x0x0 pllcon xxxx xx00 plldiv 0000 0000 wdtrst xxxx xxxx wdtprg xxxx x000 a7h 98h scon 0000 0000 sbuf xxxx xxxx brl 0000 0000 bdrcon xxx0 0000 kbls 0000 0000 kbe 0000 0000 kbf 0000 0000 9fh 90h p1 1111 1111 sscon 0000 0000 sscs 1111 1000 ssdat 1111 1111 ssadr 1111 1110 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr xx0x 0000 ckcon0 0000 0000 8fh 80h p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 00x1 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f reserved
20 7683c?usb?11/07 at83c5134/35/36 table 7-2. c51 core sfrs table 7-3. i/o port sfrs mnemonic add name 7 6 5 4 3 2 1 0 acc e0h accumulator b f0h b register psw d0h program status word sp 81h stack pointer lsb of spx dpl 82h data pointer low byte lsb of dptr dph 83h data pointer high byte msb of dptr mnemonic add name 7 6 5 4 3 2 1 0 p0 80h port 0 p1 90h port 1 p2 a0h port 2 p3 b0h port 3 p4 c0h port 4 (2bits) table 7-4. timer sfr?s mnemonic add name 7 6 5 4 3 2 1 0 th0 8ch timer/counter 0 high byte tl0 8ah timer/counter 0 low byte th1 8dh timer/counter 1 high byte tl1 8bh timer/counter 1 low byte th2 cdh timer/counter 2 high byte tl2 cch timer/counter 2 low byte tcon 88h timer/counter 0 and 1 control tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 89h timer/counter 0 and 1 modes gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 t2con c8h timer/counter 2 control tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# t2mod c9h timer/counter 2 mode t2oe dcen
21 7683c?usb?11/07 at83c5134/35/36 rcap2h cbh timer/counter 2 reload/capture high byte rcap2l cah timer/counter 2 reload/capture low byte wdtrst a6h watchdog timer reset wdtprg a7h watchdog timer program s2 s1 s0 table 7-4. timer sfr?s (continued) mnemonic add name 7 6 5 4 3 2 1 0 table 7-5. serial i/o port sfr?s mnemonic add name 7 6 5 4 3 2 1 0 scon 98h serial control fe/sm0 sm1 sm2 ren tb8 rb8 ti ri sbuf 99h serial data buffer saden b9h slave address mask saddr a9h slave address table 7-6. baud rate generator sfr?s mnemonic add name 7 6 5 4 3 2 1 0 brl 9ah baud rate reload bdrcon 9bh baud rate control brr tbck rbck spd src table 7-7. pca sfr?s mnemo- nic add name 7 6 5 4 3 2 1 0 ccon d8h pca timer/counter control cf cr ccf4 ccf3 ccf2 ccf 1 ccf0 cmod d9h pca timer/counter mode cidl wdte cps1 cps0 ecf cl e9h pca timer/counter low byte ch f9h pca timer/counter high byte ccapm 0 ccapm 1 ccapm 2 ccapm 3 ccapm 4 dah dbh dch ddh deh pca timer/counter mode 0 pca timer/counter mode 1 pca timer/counter mode 2 pca timer/counter mode 3 pca timer/counter mode 4 ecom0 ecom1 ecom2 ecom3 ecom4 capp0 capp1 capp2 capp3 capp4 capn0 capn1 capn2 capn3 capn4 mat0 mat1 mat2 mat3 mat4 tog0 tog1 tog2 tog3 tog4 pwm0 pwm1 pwm2 pwm3 pwm4 eccf0 eccf1 eccf2 eccf3 eccf4
22 7683c?usb?11/07 at83c5134/35/36 ccap0 h ccap1 h ccap2 h ccap3 h ccap4 h fah fbh fch fdh feh pca compare capture module 0 h pca compare capture module 1 h pca compare capture module 2 h pca compare capture module 3 h pca compare capture module 4 h ccap0h7 ccap1h7 ccap2h7 ccap3h7 ccap4h7 ccap0h6 ccap1h6 ccap2h6 ccap3h6 ccap4h6 ccap0h5 ccap1h5 ccap2h5 ccap3h5 ccap4h5 ccap0h4 ccap1h4 ccap2h4 ccap3h4 ccap4h4 ccap0h3 ccap1h3 ccap2h3 ccap3h3 ccap4h3 ccap0h2 ccap1h2 ccap2h2 ccap3h2 ccap4h2 ccap0h1 ccap1h1 ccap2h1 ccap3h1 ccap4h1 ccap0h0 ccap1h0 ccap2h0 ccap3h0 ccap4h0 ccap0l ccap1l ccap2l ccap3l ccap4l eah ebh ech edh eeh pca compare capture module 0 l pca compare capture module 1 l pca compare capture module 2 l pca compare capture module 3 l pca compare capture module 4 l ccap0l7 ccap1l7 ccap2l7 ccap3l7 ccap4l7 ccap0l6 ccap1l6 ccap2l6 ccap3l6 ccap4l6 ccap0l5 ccap1l5 ccap2l5 ccap3l5 ccap4l5 ccap0l4 ccap1l4 ccap2l4 ccap3l4 ccap4l4 ccap0l3 ccap1l3 ccap2l3 ccap3l3 ccap4l3 ccap0l2 ccap1l2 ccap2l2 ccap3l2 ccap4l2 ccap0l1 ccap1l1 ccap2l1 ccap3l1 ccap4l1 ccap0l0 ccap1l0 ccap2l0 ccap3l0 ccap4l0 table 7-7. pca sfr?s mnemo- nic add name 7 6 5 4 3 2 1 0 table 7-8. interrupt sfr?s mnemo- nic add name 7 6 5 4 3 2 1 0 ien0 a8h interrupt enable control 0 ea ec et2 es et1 ex1 et0 ex0 ien1 b1h interrupt enable control 1 eusb espi etwi ekb ipl0 b8h interrupt priority control low 0 ppcl pt2l psl p t1l px1l pt0l px0l iph0 b7h interrupt priority control high 0 ppch pt2h psh pt1h px1h pt0h px0h ipl1 b2h interrupt priority control low 1 pusbl pspil ptwil pkbl iph1 b3h interrupt priority control high 1 pusbh pspih ptwih pkbh table 7-9. pll sfrs mnemonic add name 7 6 5 4 3 2 1 0 pllcon a3h pll control ext48 pllen plock plldiv a4h pll divider r3 r2 r1 r0 n3 n2 n1 n0 table 7-10. keyboard sfrs mnemonic add name 7 6 5 4 3 2 1 0 kbf 9eh keyboard flag register kbf7 kbf6 kbf5 kbf4 kbf3 kbf2 kbf1 kbf0 kbe 9dh keyboard input enable register kbe7 kbe6 kbe5 kbe4 kbe3 kbe2 kbe1 kbe0
23 7683c?usb?11/07 at83c5134/35/36 kbls 9ch keyboard level selector register kbls7 kbls6 kbls5 kbls4 kbls3 kbls2 kbls1 kbls0 table 7-10. keyboard sfrs mnemonic add name 7 6 5 4 3 2 1 0 table 7-11. twi sfrs mnemonic add name 7 6 5 4 3 2 1 0 sscon 93h synchronous serial control cr2 ssie sta sto si aa cr1 cr0 sscs 94h synchronous serial control-status sc4 sc3 sc2 sc1 sc0 - - - ssdat 95h synchronous serial data sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 ssadr 96h synchronous serial address a7 a6 a5 a4 a3 a2 a1 a0 table 7-12. spi sfrs mnemonic add name 7 6 5 4 3 2 1 0 spcon c3h serial peripheral control spr2 spen ssdis mstr cpol cpha spr1 spr0 spsta c4h serial peripheral status-control spif wcol sserr modf - - - - spdat c5h serial peripheral data r7 r6 r5 r4 r3 r2 r1 r0 table 7-13. usb sfr?s mnemonic add name 7 6 5 4 3 2 1 0 usbcon bch usb global control usbe suspclk sdrmwu p detach uprsm rmwupe confg fadden usbaddr c6h usb address fen uadd6 uadd5 uadd4 uadd3 uadd2 ua dd1 uadd0 usbint bdh usb global interrupt - - wupcpu eorint sofint - - spint usbien beh usb global interrupt enable - - ewupcp u eeorint esofint - - espint uepnum c7h usb endpoint number - - - - epnum3 epnum2 epnum1 e pnum0 uepconx d4h usb endpoint x control epen - - - dtgl epdir ept ype1 eptype0 uepstax ceh usb endpoint x status dir rxoutb1 stallrq txr dy stlcrc rxsetup rxoutb0 txcmp ueprst d5h usb endpoint reset - - ep5rst ep4rst ep3rst ep2r st ep1rst ep0rst uepint f8h usb endpoint interrupt - - ep5int ep4int ep3int ep2int ep1int ep0int uepien c2h usb endpoint interrupt enable - - ep5inte ep4inte ep3inte ep2inte ep1inte ep0inte uepdatx cfh usb endpoint x fifo data fdat7 fdat6 fdat5 fdat4 fdat3 fdat2 fdat1 fdat0
24 7683c?usb?11/07 at83c5134/35/36 ubyctlx e2h usb byte counter low (ep x) byct7 byct6 byct5 byct4 byct3 byct2 byct1 byct0 ubycthx e3h usb byte counter high (ep x) - - - - - byct10 byct9 byct8 ufnuml bah usb frame number low fnum7 fnum6 fnum5 fnum4 fnum3 fnum2 fnum1 fnum0 ufnumh bbh usb frame number high - - crcok crcerr - fnum10 fnum9 fnum8 table 7-13. usb sfr?s mnemonic add name 7 6 5 4 3 2 1 0 table 7-14. other sfr?s mnemonic add name 7 6 5 4 3 2 1 0 pcon 87h power control smod1 smod0 - pof gf1 gf0 pd idl auxr 8eh auxiliary register 0 dpu - m0 - xrs1 xrs2 extram a0 auxr1 a2h auxiliary register 1 - - enboot - gf3 - - dps ckcon0 8fh clock control 0 twix2 wdx2 pcax2 six2 t2x2 t1x2 t 0x2 x2 ckcon1 afh clock control 1 - - - - - - - spix2 ledcon f1h led control led3 led2 led1 led0
25 7683c?usb?11/07 at83c5134/35/36 8. program/code memory the at83c5134/35/36 implement 16 or 32 kbytes of on -chip program/code memory. figure 8-1 shows the split of internal and external program/co de memory spaces depending on the product. figure 8-1. program/code memory organization note: if the program executes exclusively from on-ch ip code memory (not from external memory), beware of executing code from the upper byte of on- chip memory and thereby disrupting i/o ports 0 and 2 due to external prefetch. fetching code con stant from this location does not affect ports 0 and 2. 8.1 external code memory access 8.1.1 memory interface the external memory interface comprises the externa l bus (port 0 and port 2) as well as the bus control signals (psen , and ale). figure 8-2 shows the structure of the external addre ss bus. p0 carries address a7:0 while p2 carries address a15:8. data d7:0 is multiplexed wit h a7:0 on p0. table 8-1 describes the exter- nal memory interface signals. figure 8-2. external code memory interface structure 0000h 32 kbytes 7fffh rom 32 kbytes external code ffffh 8000h 0000h 16 kbytes 3fffh rom 48 kbytes external code ffffh 4000h at83c5135 at83c5136 flash eprom at89c5131 p2 p0 ad7:0 a15:8 a7:0 a15:8 d7:0 a7:0 ale latch oe psen
26 7683c?usb?11/07 at83c5134/35/36 table 8-1. external data memory interface signals 8.1.2 external bus cycles this section describes the bus cycles the at83c5134 /35/36 executes to fetch code (see figure 8-3) in the external program/code memory. external memory cycle takes 6 cpu clock periods. th is is equivalent to 12 oscillator clock peri- ods in standard mode or 6 oscillator clock periods in x2 mode. for further information on x2 mode (see the clock section). for simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and do not provide precise timing information. figure 8-3. external code fetch waveforms signal name type description alternate function a15:8 o address lines upper address lines for the external bus. p2.7:0 ad7:0 i/o address/data lines multiplexed lower address lines and data for the ex ternal memory. p0.7:0 ale o address latch enable ale signals indicates that valid address informatio n are available on lines ad7:0. - psen o program store enable output this signal is active low during external code fetc h or external code read (movc instruction). - ale p0 p2 psen pcl pch pch pcl d7:0 d7:0 pch d7:0 cpu clock
27 7683c?usb?11/07 at83c5134/35/36 9. at89c5131 rom 9.1 rom structure the at89c5131 rom memory is divided in two differen t arrays: ? the code array: 16-32 kbytes. ? the configuration byte:1 byte. 9.1.1 hardware configuration byte the configuration byte sets the starting microcontr oller options and the security levels. the starting default options are x1 mode, oscillato r a. hsb = xxxx xx11b 9.2 rom lock system the program lock system, when programmed, protects the on-chip program against software piracy. table 9-1. hardware security byte (hsb) hsb (s:efh) power configuration register 7 6 5 4 3 2 1 0 - - oscon1 oscon0 - - lb1 lb0 bit number bit mnemonic description 7 - reserved 6 - reserved 5-4 oscon1-0 oscillator control bits these two bits are used to control the oscillator i n order to reduce consumption. oscon1 oscon0 description 1 1 the oscillator is configured to run from 0 to 32 mhz 1 0 the oscillator is configured to run from 0 to 16 mhz 0 1 the oscillator is configured to run from 0 to 8 mhz 0 0 this configuration shouldn?t be set 3 - reserved 2 - reserved 1-0 lb1-0 user program lock bits see table 9-2 on page 28
28 7683c?usb?11/07 at83c5134/35/36 9.2.1 program rom lock bits the lock bits when programmed according to table 9-2 will provide different level of protection for the on-chip code and data. u: unprogrammed p: programmed table 9-2. program lock bits program lock bits protection description security level lb1 lb0 1 u u no program lock feature enabled. 3 p u reading rom data from programmer is disabled.
29 7683c?usb?11/07 at83c5134/35/36 10. stacked eeprom 10.1 overview the at83c5134/35/36 features a stacked 2-wire seria l data eeprom. the data eeprom allows to save from 512 byte for at24c04 version up to 32 kbytes for at24c256 version. the eeprom is internally connected to the microcontroll er on sda and scl pins. 10.2 protocol in order to access this memory, it is necessary to use software subroutines according to the at 24cx x da tashee t. never thele ss , beca use the in te rn al pul l-u p re sis tors of the at83c5134/35/36 is quite high (around 100k ), the protocol should be slowed in order to be sure that the sda pin can rise to the high level be fore reading it. another solution to keep the access to the eeprom i n specification is to work with a software pull-up. using a software pull-up, consists of forcing a low level at the output pin of the microcontroller before configuring it as an input (high level). the c51 the ports are ?quasi-bidirectional? ports. it means that the ports can be configured as output low or as input high. in case a port is conf igured as an output low, it can sink a current and all internal pull-ups are disconnected. in case a port is configured as an input high, it is pulled up with a strong pull-up (a few hundreds ohm s resistor) for 2 clock periods. then, if the port is externally connected to a low level, it is only kept high with a weak pull up (around 100k ), and if not, the high level is latched high thank s to a medium pull (around 10k ). thus, when the port is configured as an input, and when this input has been read at a low level, there is a pull-up of around 100k , which is quite high, to quickly load the sda capa citance. so in order to help the reading of a high level just a fter the reading of a low level, it is possible to force a transition of the sda port from an input st ate (1), to an output low state (0), followed by a new transition from this output low state to input state; in this case, the high pull-up has been replaced with a low pull-up which warranties a good reading of the data.
30 7683c?usb?11/07 at83c5134/35/36 11. on-chip expanded ram (eram) the at83c5134/35/36 provides additional bytes of ra ndom access memory (ram) space for increased data parameters handling and high level l anguage usage. at83c5134/35/36 devices have an expanded ram in the external data space; maximum size and location are described in table 11-1. the at83c5134/35/36 has on-chip data memory which i s mapped into the following four sepa- rate segments. 1. the lower 128 bytes of ram (addresses 00h to 7fh) are directly and indirectly addressable. 2. the upper 128 bytes of ram (addresses 80h to ffh) are indirectly addressable only. 3. the special function registers, sfrs, (addresses 80h to ffh) are directly address- able only. 4. the expanded ram bytes are indirectly accessed by movx instructions, and with the extram bit cleared in the auxr register (see table 1 1-1) the lower 128 bytes can be accessed by either direc t or indirect addressing. the upper 128 bytes can be accessed by indirect addressing only. the upper 128 bytes occupy the same address space as the sfr. that means they have the same address, but are physically sepa- rate from sfr space. figure 11-1. internal and external data memory address when an instruction accesses an internal location a bove address 7fh, the cpu knows whether the access is to the upper 128 bytes of data ram or to sfr space by the addressing mode used in the instruction. table 11-1. description of expanded ram part number eram size address start end at83c5134/35/36 1024 00h 3ffh eram upper 128 bytes internal ram lower 128 bytes internal ram special function register 80h 80h 00 0ffh or 3ffh(*) 0ffh 00 0ffh external data memory 0000 00ffh up to 03ffh (*) 0ffffh indirect accesses direct accesses direct or indirect accesses 7fh (*) depends on xrs1..0
31 7683c?usb?11/07 at83c5134/35/36 ? instructions that use direct addressing access sfr space. for example: mov 0a0h, # data, accesses the sfr at location 0a0h (which is p2). ? instructions that use indirect addressing access t he upper 128 bytes of data ram. for example: mov atr0, # data where r0 contains 0a0h, a ccesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). ? the eram bytes can be accessed by indirect address ing, with extram bit cleared and movx instructions. this part of memory which is phy sically located on-chip, logically occupies the first bytes of external data memory. t he bits xrs0 and xrs1 are used to hide a part of the available eram as explained in table 11- 1. this can be useful if external peripherals are mapped at addresses already used by the internal eram. ? with extram = 0, the eram is indirectly addressed, using the movx i nstruction in combination with any of the registers r0, r1 of the selected bank or dptr. an access to eram will not affect ports p0, p2, p3.6 (wr) and p3 .7 (rd). for example, with extram = 0, movx atr0, # data where r0 contains 0a0h, access es the eram at address 0a0h rather than external memory. an access to external data me mory locations higher than the accessible size of the eram will be performed with the movx dptr instructions in the same way as in the standard 80c51, with p0 and p2 as dat a/address busses, and p3.6 and p3.7 as write and read timing signals. accesses to eram above 0ffh can only be done by the use of dptr. ? with extram = 1 , movx @ri and movx @dptr will be similar to the st andard 80c51. movx at ri will provide an eight-bit address multip lexed with data on port0 and any output port pins can be used to output higher order addres s bits. this is to provide the external paging capability. movx @dptr will generate a sixte en-bit address. port2 outputs the high- order eight address bits (the contents of dph) whil e port0 multiplexes the low-order eight address bits (dpl) with data. movx at ri and movx @ dptr will generate either read or write signals on p3.6 (wr ) and p3.7 (rd ). the stack pointer (sp) may be located anywhere in t he 256 bytes ram (lower and upper ram) internal data memory. the stack may not be located in the eram. the m0 bit allows to stretch the eram timings; if m 0 is set, the read and write pulses are extended from 6 to 30 clock periods. this is useful to access external slow peripherals. table 11-2. auxr register auxr - auxiliary register (8eh) 7 6 5 4 3 2 1 0 dpu - m0 - xrs1 xrs0 extram ao bit number bit mnemonic description 7 dpu disable weak pull up cleared to enabled weak pull up on standard ports. set to disable weak pull up on standard ports. 6 - reserved the value read from this bit is indeterminate. do n ot set this bit 5 m0 pulse length cleared to stretch movx control: the rd and the wr pulse length is 6 clock periods (default). set to stretch movx control: the rd and the wr pulse length is 30 clock periods.
32 7683c?usb?11/07 at83c5134/35/36 reset value = 0x0x 1100b not bit addressable 4 - reserved the value read from this bit is indeterminate. do n ot set this bit 3 xrs1 eram size xrs1 xrs0 eram size 0 0 256 bytes 0 1 512 bytes 1 0 768 bytes 1 1 1024 bytes (default) 2 xrs0 1 extram extram bit cleared to access internal eram using movx at ri at dptr. set to access external memory. 0 ao ale output bit cleared, ale is emitted at a constant rate of 1/6 t he oscillator frequency (or 1/3 if x2 mode is used) (default). set, ale is active only when a movx or movc instruc tion is used. bit number bit mnemonic description
33 7683c?usb?11/07 at83c5134/35/36 12. timer 2 the timer 2 in the at83c5134/35/36 is the standard c52 timer 2. it is a 16-bit timer/counter: the count is maintained by two cascaded eight-bit t imer registers, th2 and tl2. it is controlled by t2con (table 12-1) and t2mod (table 12-2) register s. timer 2 operation is similar to timer 0 and timer 1. c/t2 selects f osc /12 (timer operation) or external pin t2 (counter o peration) as the timer clock input. setting tr2 allows tl2 to be incremented by the selected input. timer 2 has 3 operating modes: capture, auto reload and baud rate generator. these modes are selected by the combination of rclk, tclk and c p/rl2 (t2con). refer to the atmel 8-bit microcontroller hardware d ocumentation for the description of capture and baud rate generator modes. timer 2 includes the following enhancements: ? auto-reload mode with up or down counter ? programmable clock-output 12.1 auto-reload mode the auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. if dcen bit in t2mod is cleared, timer 2 be haves as in 80c52 (refer to the atmel 8-bit microcontroller hardware description). if dcen bit is set, timer 2 acts as an up/down timer/counter as shown in figure 12-1 . in this mode the t2ex pin controls the direction of count. when t2ex is high, timer 2 counts up. timer overflo w occurs at ffffh which sets the tf2 flag and generates an interrupt request. the overflow al so causes the 16-bit value in rcap2h and rcap2l registers to be loaded into the timer regist ers th2 and tl2. when t2ex is low, timer 2 counts down. timer underf low occurs when the count in the timer registers th2 and tl2 equals the value stored in rc ap2h and rcap2l registers. the under- flow sets tf2 flag and reloads ffffh into the timer registers. the exf2 bit toggles when timer 2 overflows or unde rflows according to the direction of the count. exf2 does not generate any interrupt. this b it can be used to provide 17-bit resolution.
34 7683c?usb?11/07 at83c5134/35/36 figure 12-1. auto-reload mode up/down counter (dcen = 1) 12.2 programmable clock output in the clock-out mode, timer 2 operates as a 50%-du ty-cycle, programmable clock generator (see figure 12-2). the input clock increments tl2 at frequency f clk periph /2. the timer repeat- edly counts to overflow from a loaded value. at ove rflow, the contents of rcap2h and rcap2l registers are loaded into th2 and tl2. in this mode , timer 2 overflows do not generate inter- rupts. the following formula gives the clock-out fr equency as a function of the system oscillator frequency and the value in the rcap2h and rcap2l re gisters for a 16 mhz system clock, timer 2 has a programmab le frequency range of 61 hz (f clk periph /2 16) to 4 mhz (f clk periph /4). the generated clock signal is brought out to t 2 pin (p1.0). timer 2 is programmed for the clock-out mode as fol lows: ? set t2oe bit in t2mod register. ? clear c/t2 bit in t2con register. ? determine the 16-bit reload value from the formula and enter it in rcap2h/rcap2l registers. ? enter a 16-bit initial value in timer registers th 2/tl2. it can be the same as the reload value or a different one depending on the application. ? to start the timer, set tr2 run control bit in t2c on register. (down counting reload value) c/t 2 tf2 tr2 t2 exf2 th2 (8-bit) tl2 (8-bit) rcap2h (8-bit) rcap2l (8-bit) ffh (8-bit) ffh (8-bit) toggle (up counting reload value) timer 2 interrupt f clk periph 0 1 t2con t2con t2con t2con t2ex: if dcen = 1, 1 = up if dcen = 1, 0 = down if dcen = 0, up counting : 6 clock outfrequency ? f clkperiph 4 65536 rcap 2 h ? rcap 2 l M ( ) --------------------------------------------------- -------------------------------------- =
35 7683c?usb?11/07 at83c5134/35/36 it is possible to use timer 2 as a baud rate genera tor and a clock generator simultaneously. for this configuration, the baud rates and clock freque ncies are not independent since both func- tions use the values in the rcap2h and rcap2l regis ters. figure 12-2. clock-out mode c/t2 = 0 : 6 exf2 tr2 overflow t2ex th2 (8-bit) tl2 (8-bit) timer 2 rcap2h (8-bit) rcap2l (8-bit) t2oe t2 f clk periph t2con t2con t2con t2mod interrupt q d toggle exen2
36 7683c?usb?11/07 at83c5134/35/36 reset value = 0000 0000b bit addressable table 12-1. t2con register t2con - timer 2 control register (c8h) 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# bit number bit mnemonic description 7 tf2 timer 2 overflow flag must be cleared by software. set by hardware on timer 2 overflow, if rclk = 0 an d tclk = 0. 6 exf2 timer 2 external flag set when a capture or a reload is caused by a negat ive transition on t2ex pin if exen2 = 1. when set, causes the cpu to vector to timer 2 inter rupt routine when timer 2 interrupt is enabled. must be cleared by software. exf2 doesn?t cause an interrupt in up/down counter mode (dcen = 1). 5 rclk receive clock bit cleared to use timer 1 overflow as receive clock fo r serial port in mode 1 or 3. set to use timer 2 overflow as receive clock for se rial port in mode 1 or 3. 4 tclk transmit clock bit cleared to use timer 1 overflow as transmit clock f or serial port in mode 1 or 3. set to use timer 2 overflow as transmit clock for s erial port in mode 1 or 3. 3 exen2 timer 2 external enable bit cleared to ignore events on t2ex pin for timer 2 op eration. set to cause a capture or reload when a negative tr ansition on t2ex pin is detected, if timer 2 is not used to clock the serial port. 2 tr2 timer 2 run control bit cleared to turn off timer 2. set to turn on timer 2. 1 c/t2# timer/counter 2 select bit cleared for timer operation (input from internal cl ock system: f clk periph ). set for counter operation (input from t2 input pin, falling edge trigger). must be 0 for clock out mode. 0 cp/rl2# timer 2 capture/reload bit if rclk = 1 or tclk = 1, cp/rl2# is ignored and tim er is forced to auto-reload on timer 2 overflow. cleared to auto-reload on timer 2 overflows or nega tive transitions on t2ex pin if exen2 = 1. set to capture on negative transitions on t2ex pin if exen2 = 1.
37 7683c?usb?11/07 at83c5134/35/36 reset value = xxxx xx00b not bit addressable table 12-2. t2mod register t2mod - timer 2 mode control register (c9h) 7 6 5 4 3 2 1 0 - - - - - - t2oe dcen bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do n ot set this bit. 6 - reserved the value read from this bit is indeterminate. do n ot set this bit. 5 - reserved the value read from this bit is indeterminate. do n ot set this bit. 4 - reserved the value read from this bit is indeterminate. do n ot set this bit. 3 - reserved the value read from this bit is indeterminate. do n ot set this bit. 2 - reserved the value read from this bit is indeterminate. do n ot set this bit. 1 t2oe timer 2 output enable bit cleared to program p1.0/t2 as clock input or i/o po rt. set to program p1.0/t2 as clock output. 0 dcen down counter enable bit cleared to disable timer 2 as up/down counter. set to enable timer 2 as up/down counter.
38 7683c?usb?11/07 at83c5134/35/36 13. programmable counter array (pca) the pca provides more timing capabilities with less cpu intervention than the standard timer/counters. its advantages include reduced soft ware overhead and improved accuracy. the pca consists of a dedicated timer/counter which ser ves as the time base for an array of five compare/capture modules. its clock input can be pro grammed to count any one of the following signals: ? peripheral clock frequency (f clk periph ) 6 ? peripheral clock frequency (f clk periph ) 2 ? timer 0 overflow ? external input on eci (p1.2) each compare/capture modules can be programmed in a ny one of the following modes: ? rising and/or falling edge capture, ? software timer ? high-speed output, or ? pulse width modulator module 4 can also be programmed as a watchdog timer (see section "pca watchdog timer", page 48). when the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generat ed when the module executes its function. all five modules plus the pca timer overflow share one interrupt vector. the pca timer/counter and compare/capture modules s hare port 1 for external i/o. these pins are listed below. if the port pin is not used for t he pca, it can still be used for standard i/o. the pca timer is a common time base for all five mo dules (see figure 13-1). the timer count source is determined from the cps1 and cps0 bits in the cmod register (table 13-1) and can be programmed to run at: ? 1/6 the peripheral clock frequency (f clk periph ) . ? 1/2 the peripheral clock frequency (f clk periph ) . ? the timer 0 overflow ? the input on the eci pin (p1.2) pca component external i/o pin 16-bit counter p1.2/eci 16-bit module 0 p1.3/cex0 16-bit module 1 p1.4/cex1 16-bit module 2 p1.5/cex2 16-bit module 3 p1.6/cex3 16-bit module 4 p1.7/cex4
39 7683c?usb?11/07 at83c5134/35/36 figure 13-1. pca timer/counter table 13-1. cmod register cmod - pca counter mode register (d9h) cidl cps1 cps0 ecf it ch cl 16 bit up counter to pca modules f clk periph /6 f clk periph /2 t0 ovf p1.2 idle cmod 0xd9 wdte cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 overflow 7 6 5 4 3 2 1 0 cidl wdte - - - cps1 cps0 ecf bit number bit mnemonic description 7 cidl counter idle control cleared to program the pca counter to continue func tioning during idle mode. set to program pca to be gated off during idle. 6 wdte watchdog timer enable cleared to disable watchdog timer function on pca m odule 4. set to enable watchdog timer function on pca module 4. 5 - reserved the value read from this bit is indeterminate. do n ot set this bit. 4 - reserved the value read from this bit is indeterminate. do n ot set this bit. 3 - reserved the value read from this bit is indeterminate. do n ot set this bit. 2 cps1 pca count pulse select cps1 cps0 selected pca input 0 0 internal clock f clk periph /6 0 1 internal clock f clk periph /2 1 0 timer 0 overflow 1 1 external clock at eci/p1.2 pin (max rate = f clk periph / 4) 1 cps0 0 ecf pca enable counter overflow interrupt cleared to disable cf bit in ccon to inhibit an int errupt. set to enable cf bit in ccon to generate an interru pt.
40 7683c?usb?11/07 at83c5134/35/36 reset value = 00xx x000b not bit addressable the cmod register includes three additional bits as sociated with the pca (see figure 13-1 and table 13-1). ? the cidl bit allows the pca to stop during idle mo de. ? the wdte bit enables or disables the watchdog func tion on module 4. ? the ecf bit when set causes an interrupt and the p ca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. the ccon register contains the run control bit for the pca and the flags for the pca timer (cf) and each module (see table 13-2). ? bit cr (ccon.6) must be set by software to run the pca. the pca is shut off by clearing this bit. ? bit cf: the cf bit (ccon.7) is set when the pca co unter overflows and an interrupt will be generated if the ecf bit in the cmod register is se t. the cf bit can only be cleared by software. ? bits 0 through 4 are the flags for the modules (bi t 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a captur e occurs. these flags can only be cleared by software. table 13-2. ccon register ccon - pca counter control register (d8h) 7 6 5 4 3 2 1 0 cf cr ? ccf4 ccf3 ccf2 ccf1 ccf0 bit number bit mnemonic description 7 cf pca counter overflow flag set by hardware when the counter rolls over. cf fla gs an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but ca n only be cleared by software. 6 cr pca counter run control bit must be cleared by software to turn the pca counter off. set by software to turn the pca counter on. 5 ? reserved the value read from this bit is indeterminate. do n ot set this bit. 4 ccf4 pca module 4 interrupt flag must be cleared by software. set by hardware when a match or capture occurs. 3 ccf3 pca module 3 interrupt flag must be cleared by software. set by hardware when a match or capture occurs. 2 ccf2 pca module 2 interrupt flag must be cleared by software. set by hardware when a match or capture occurs.
41 7683c?usb?11/07 at83c5134/35/36 reset value = 000x 0000b not bit addressable the watchdog timer function is implemented in modul e 4 (see figure 13-4). the pca interrupt system is shown in figure 13-2. figure 13-2. pca interrupt system pca modules: each one of the five compare/capture modules has si x possible functions. it can perform: ? 16-bit capture, positive-edge triggered ? 16-bit capture, negative-edge triggered ? 16-bit capture, both positive and negative-edge tr iggered ? 16-bit software timer ? 16-bit high-speed output ? 8-bit pulse width modulator in addition, module 4 can be used as a watchdog tim er. each module in the pca has a special function regis ter associated with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. (see table 13-3). the registers contain the bits that control the mode that each module will op erate in. 1 ccf1 pca module 1 interrupt flag must be cleared by software. set by hardware when a match or capture occurs. 0 ccf0 pca module 0 interrupt flag must be cleared by software. set by hardware when a match or capture occurs. bit number bit mnemonic description cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 module 4 module 3 module 2 module 1 module 0 ecf pca timer/counter eccfn ccapmn.0 cmod.0 ie.6 ie.7 to interrupt priority decoder ec ea
42 7683c?usb?11/07 at83c5134/35/36 ? the eccf bit (ccapmn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the ccf flag in the ccon sfr to generate an interrupt w hen a match or compare occurs in the associated module. ? pwm (ccapmn.1) enables the pulse width modulation mode. ? the tog bit (ccapmn.2) when set causes the cex out put associated with the module to toggle when there is a match between the pca counte r and the module's capture/compare register. ? the match bit mat (ccapmn.3) when set will cause t he ccfn bit in the ccon register to be set when there is a match between the pca counter a nd the module's capture/compare register. ? the next two bits capn (ccapmn.4) and capp (ccapmn .5) determine the edge that a capture input will be active on. the capn bit enabl es the negative edge, and the capp bit enables the positive edge. if both bits are set bot h edges will be enabled and a capture will occur for either transition. ? the last bit in the register ecom (ccapmn.6) when set enables the comparator function. table 13-4 shows the ccapmn settings for the various pca functions. table 13-3. ccapmn registers (n = 0-4) ccapm0 - pca module 0 compare/capture control regis ter (0dah) ccapm1 - pca module 1 compare/capture control regis ter (0dbh) ccapm2 - pca module 2 compare/capture control regis ter (0dch) ccapm3 - pca module 3 compare/capture control regis ter (0ddh) ccapm4 - pca module 4 compare/capture control regis ter (0deh) 7 6 5 4 3 2 1 0 - ecomn cappn capnn matn togn pwmn eccfn bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do n ot set this bit. 6 ecomn enable comparator cleared to disable the comparator function. set to enable the comparator function. 5 cappn capture positive cleared to disable positive edge capture. set to enable positive edge capture. 4 capnn capture negative cleared to disable negative edge capture. set to enable negative edge capture. 3 matn match when matn = 1, a match of the pca counter with this module's compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. 2 togn toggle when togn = 1, a match of the pca counter with this module's compare/capture register causes the cexn pin to toggle.
43 7683c?usb?11/07 at83c5134/35/36 reset value = x000 0000b not bit addressable table 13-4. pca module modes (ccapmn registers) there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store t he 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output (see table 13-5 and table 13-6) 1 pwmn pulse width modulation mode cleared to disable the cexn pin to be used as a pul se width modulated output. set to enable the cexn pin to be used as a pulse wi dth modulated output. 0 eccfn enable ccf interrupt cleared to disable compare/capture flag ccfn in the ccon register to generate an interrupt. set to enable compare/capture flag ccfn in the ccon register to generate an interrupt. ecomn cappn capnn matn togn pwmm eccfn module function 0 0 0 0 0 0 0 no operation x 1 0 0 0 0 x 16-bit capture by a positive-edge trigger on cexn x 0 1 0 0 0 x 16-bit capture by a negative trigger on cexn x 1 1 0 0 0 x 16-bit capture by a transition on cexn 1 0 0 1 0 0 x 16-bit software timer/compare mode. 1 0 0 1 1 0 x 16-bit high speed output 1 0 0 0 0 1 0 8-bit pwm 1 0 0 1 x 0 x watchdog timer (module 4 only) bit number bit mnemonic description
44 7683c?usb?11/07 at83c5134/35/36 table 13-5. ccapnh registers (n = 0-4) ccap0h - pca module 0 compare/capture control regis ter high (0fah) ccap1h - pca module 1 compare/capture control regis ter high (0fbh) ccap2h - pca module 2 compare/capture control regis ter high (0fch) ccap3h - pca module 3 compare/capture control regis ter high (0fdh) ccap4h - pca module 4 compare/capture control regis ter high (0feh) reset value = xxxx xxxxb not bit addressable table 13-6. ccapnl registers (n = 0-4) ccap0l - pca module 0 compare/capture control regis ter low (0eah) ccap1l - pca module 1 compare/capture control regis ter low (0ebh) ccap2l - pca module 2 compare/capture control regis ter low (0ech) ccap3l - pca module 3 compare/capture control regis ter low (0edh) ccap4l - pca module 4 compare/capture control regis ter low (0eeh) reset value = xxxx xxxxb not bit addressable table 13-7. ch register ch - pca counter register high (0f9h) reset value = 0000 0000b not bit addressable 7 6 5 4 3 2 1 0 - - - - - - - - bit number bit mnemonic description 7 - 0 - pca module n compare/capture control ccapnh value 7 6 5 4 3 2 1 0 - - - - - - - - bit number bit mnemonic description 7 - 0 - pca module n compare/capture control ccapnl value 7 6 5 4 3 2 1 0 - - - - - - - - bit number bit mnemonic description 7 - 0 - pca counter ch value
45 7683c?usb?11/07 at83c5134/35/36 table 13-8. cl register cl - pca counter register low (0e9h) reset value = 0000 0000b not bit addressable 13.1 pca capture mode to use one of the pca modules in the capture mode e ither one or both of the ccapm bits capn and capp for that module must be set. the exte rnal cex input for the module (on port 1) is sampled for a transition. when a valid transitio n occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the modu le's capture registers (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated (se e figure 13-3). figure 13-3. pca capture mode 13.2 16-bit software timer/compare mode the pca modules can be used as software timers by s etting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module's capture regis- ters and when a match occurs an interrupt will occu r if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set (see figure 13-4). 7 6 5 4 3 2 1 0 - - - - - - - - bit number bit mnemonic description 7 - 0 - pca counter cl value cf cr ccon 0xd8 ch cl ccapnh ccapnl ccf4 ccf3 ccf2 ccf1 ccf0 pca it pca counter/timer ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn cex.n capture
46 7683c?usb?11/07 at83c5134/35/36 figure 13-4. pca compare mode and pca watchdog timer note: 1. only for module 4 before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, other- wise an unwanted match could happen. writing to cca pnh will set the ecom bit. once ecom set, writing ccapnl will clear ecom so th at an unwanted match doesn?t occur while modifying the compare value. writing to ccapn h will set ecom. for this reason, user software should write ccapnl first, and then ccapnh . of course, the ecom bit can still be controlled by accessing to ccapmn register. 13.3 high speed output mode in this mode, the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the module 's capture registers. to activate this mode the tog, mat, and ecom bits in the module's cc apmn sfr must be set (see figure 13-5). a prior write must be done to ccapnl and ccapnh bef ore writing the ecomn bit. ch cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 16-bit comparator match ccon 0xd8 pca it enable pca counter/timer reset (1) cidl cps1 cps0 ecf cmod 0xd9 wdte reset write to ccapnl write to ccapnh cf ccf2 ccf1 ccf0 cr ccf3 ccf4 1 0
47 7683c?usb?11/07 at83c5134/35/36 figure 13-5. pca high-speed output mode before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, other- wise an unwanted match could happen. once ecom set, writing ccapnl will clear ecom so th at an unwanted match doesn?t occur while modifying the compare value. writing to ccapn h will set ecom. for this reason, user software should write ccapnl first, and then ccapnh . of course, the ecom bit can still be controlled by accessing to ccapmn register. 13.4 pulse width modulator mode all of the pca modules can be used as pwm outputs. figure 13-6 shows the pwm function. the frequency of the output depends on the source f or the pca timer. all of the modules will have the same frequency of output because they all share the pca timer. the duty cycle of each module is independently variable using the module's capture register ccapln. when the value of the pca cl sfr is less than the value in the mod ule's ccapln sfr the output will be low, when it is equal to or greater than the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. this a llows updating the pwm without glitches. the pwm and ecom bits in the module's ccapmn regist er must be set to enable the pwm mode. ch cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 16-bit comparator match cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 pca it enable cexn pca counter/timer write to ccapnh reset write to ccapnl 1 0
48 7683c?usb?11/07 at83c5134/35/36 figure 13-6. pca pwm mode 13.5 pca watchdog timer an on-board watchdog timer is available with the pc a to improve the reliability of the system without increasing chip count. watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. module 4 is the only pca module that can be programmed as a watchdog. however, this module can still be used for other modes if the watchdog is not needed. figure 13-4 shows a diagram of how the watchdog works. the user pre-loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a matc h is allowed to occur, an internal reset will be generated. this will not cause the rst pin to be driven low. in order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the pca timer 2. periodically change the pca timer value so it wil l never match the compare values, or 3. disable the watchdog by clearing the wdte bit bef ore a match occurs and then re- enable it the first two options are more reliable because the watchdog timer is never disabled as in option #3. if the program counter ever goes astray, a matc h will eventually occur and cause an internal reset. the second option is also not recommended if other pca modules are being used. remember, the pca timer is the time base for all mo dules; changing the time base for other modules would not be a good idea. thus, in most app lications the first solution is the best option. this watchdog timer won?t generate a reset out on t he reset pin. cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 8-bit comparator cexn ?0? ?1? < enable pca counter/timer overflow
49 7683c?usb?11/07 at83c5134/35/36 14. serial i/o port the serial i/o port in the at83c5134/35/36 is compa tible with the serial i/o port in the 80c52. it provides both synchronous and asynchronous commu nication modes. it operates as an uni- versal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous transmission and reception can occur simultaneously and at different baud rates. serial i/o port includes the following enhancements : ? framing error detection ? automatic address recognition 14.1 framing error detection framing bit error detection is provided for the thr ee asynchronous modes (modes 1, 2 and 3). to enable the framing bit error detection feature, set smod0 bit in pcon register (see figure 14- 1). figure 14-1. framing error block diagram when this feature is enabled, the receiver checks e ach incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the se rial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the fra ming error bit (fe) in scon register (see table 14-1 ) bit is set. software may examine fe bit after each reception to check for data errors. once set, only soft- ware or a reset can clear fe bit. subsequently rece ived frames with valid stop bits cannot clear fe bit. when fe feature is enabled, ri rises on sto p bit instead of the last data bit (see figure 14-2 and figure 14-3 ). figure 14-2. uart timings in mode 1 ri ti rb8 tb8 ren sm2 sm1 sm0/fe idl pd gf0 gf1 pof - smod0 smod1 to uart framing error control sm0 to uart mode control (smod0 = 0) set fe bit if stop bit is 0 (framing error) (smod0 = 1) scon (98h) pcon (87h) data byte ri smod0 = x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0 = 1
50 7683c?usb?11/07 at83c5134/35/36 figure 14-3. uart timings in modes 2 and 3 14.2 automatic address recognition the automatic address recognition feature is enable d when the multiprocessor communication feature is enabled (sm2 bit in scon register is set ). implemented in hardware, automatic address recognit ion enhances the multiprocessor commu- nication feature by allowing the serial port to exa mine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures tha t the cpu is not interrupted by command frames addressed to other devices. if desired, you may enable the automatic address re cognition feature in mode 1. in this configu- ration, the stop bit takes the place of the ninth d ata bit. bit ri is set only when the received command frame address matches the device?s address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broad- cast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e., setting sm2 bit in scon re gister in mode 0 has no effect). 14.2.1 given address each device has an individual address that is speci fied in saddr register; the saden register is a mask byte that contains don?t care bits (defin ed by zeros) to form the device?s given address. the don?t care bits provide the flexibilit y to address one or more slaves at a time. the following example illustrates how a given address i s formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr0101 0110b saden 1111 1100b given0101 01xxb the following is an example of how to use given add resses to address different slaves: slave a:saddr1111 0001b saden 1111 1010b given1111 0x0xb slave b:saddr1111 0011b saden 1111 1001b given1111 0xx1b ri smod0 = 0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0 = 1 fe smod0 = 1
51 7683c?usb?11/07 at83c5134/35/36 slave c:saddr1111 0011b saden 1111 1101b given1111 00x1b the saden byte is selected so that each slave may b e addressed separately. for slave a, bit 0 (the lsb) is a don?t care bit; f or slaves b and c, bit 0 is a 1. to communicate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 1; for slaves b and c, bit 1 is a don?t care bit. to communicate with slaves b and c, but not slave a, the master must send an a ddress with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master m ust send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). 14.2.2 broadcast address a broadcast address is formed from the logical or o f the saddr and saden registers with zeros defined as don?t care bits, e.g.: saddr0101 0110b saden1111 1100b broadcast = saddr or saden1111 111xb the use of don?t care bits provides flexibility in defining the broadcast address, in most applica- tions, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a:saddr1111 0001b saden 1111 1010b broadcast1111 1x11b, slave b:saddr1111 0011b saden 1111 1001b broadcast1111 1x11b, slave c:saddr = 1111 0011b saden 1111 1101b broadcast1111 1111b for slaves a and b, bit 2 is a don?t care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh. 14.2.3 reset addresses on reset, the saddr and saden registers are initial ized to 00h, i.e. the given and broadcast addresses are xxxx xxxxb (all don?t care bits). this ensures that the seria l port will reply to any address, and so, that it is backwards compatible wi th the 80c51 microcontrollers that do not support automatic address recognition.
52 7683c?usb?11/07 at83c5134/35/36 saden - slave address mask register (b9h) reset value = 0000 0000b not bit addressable saddr - slave address register (a9h) reset value = 0000 0000b not bit addressable 14.3 baud rate selection for uart for mode 1 and 3 the baud rate generator for transmit and receive cl ocks can be selected separately via the t2con and bdrcon registers. figure 14-4. baud rate selection 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 rclk / 16 rbck int_brg 0 1 timer1 0 1 0 1 timer2 int_brg timer1 timer2 timer_brg_rx rx clock / 16 0 1 timer_brg_tx tx clock tbck tclk
53 7683c?usb?11/07 at83c5134/35/36 14.3.1 baud rate selection table for uart 14.3.2 internal baud rate generator (brg) when the internal baud rate generator is used, the baud rates are determined by the brg overflow depending on the brl reload value, the val ue of spd bit (speed mode) in bdrcon register and the value of the smod1 bit in pcon reg ister. figure 14-5. internal baud rate ? the baud rate for uart is token by formula: table 14-1. scon register ? scon serial control register (98h) tclk (t2con) rclk (t2con) tbck (bdrcon) rbck (bdrcon) clock source uart tx clock source uart rx 0 0 0 0 timer 1 timer 1 1 0 0 0 timer 2 timer 1 0 1 0 0 timer 1 timer 2 1 1 0 0 timer 2 timer 2 x 0 1 0 int_brg timer 1 x 1 1 0 int_brg timer 2 0 x 0 1 timer 1 int_brg 1 x 0 1 timer 2 int_brg x x 1 1 int_brg int_brg brg 0 1 /6 brl /2 0 1 int_brg spd brr smod1 auto reload counter overflow peripheral clock 7 6 5 4 3 2 1 0 fe/sm0 sm1 sm2 ren tb8 rb8 ti ri baud_rate = 2 smod1 x f clk periph 2 x 6 (1-spd) x 16 x [256 - (brl)] (brl) = 256 - 2 smod1 x f clk periph 2 x 6 (1-spd) x 16 x baud_rate
54 7683c?usb?11/07 at83c5134/35/36 reset value = 0000 0000b bit addressable bit number bit mnemonic description 7 fe framing error bit (smod0 = 1 ) clear to reset the error state, not cleared by a va lid stop bit. set by hardware when an invalid stop bit is detecte d. smod0 must be set to enable access to the fe bit sm0 serial port mode bit 0 refer to sm1 for serial port mode selection. smod0 must be cleared to enable access to the sm0 b it 6 sm1 serial port mode bit 1 sm0 sm1 mode description baud rate 0 0 0 shift register f cpu periph /6 0 1 1 8-bit uart variable 1 0 2 9-bit uart f cpu periph/ 32 or/16 1 1 3 9-bit uart variable 5 sm2 serial port mode 2 bit/multiprocessor communication enable bit clear to disable multiprocessor communication featu re. set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. this bit should be cleared in mode 0. 4 ren reception enable bit clear to disable serial reception. set to enable serial reception. 3 tb8 transmitter bit 8/ninth bit to transmit in modes 2 and 3 clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2 rb8 receiver bit 8/ninth bit received in modes 2 and 3 cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. in mode 1, if sm2 = 0, rb8 is the received stop bit . in mode 0 rb8 is not used. 1 ti transmit interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in m ode 0 or at the beginning of the stop bit in the other modes. 0 ri receive interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in m ode 0, see figure 14-2. and figure 14- 3. in the other modes.
55 7683c?usb?11/07 at83c5134/35/36 example of computed value when x2 = 1, smod1 = 1, s pd = 1 example of computed value when x2 = 0, smod1 = 0, s pd = 0 the baud rate generator can be used for mode 1 or 3 (refer to figure 14-4.), but also for mode 0 for uart, thanks to the bit src located in bdrcon r egister (table 14-4.) 14.4 uart registers saden - slave address mask register for uart (b9h) reset value = 0000 0000b saddr - slave address register for uart (a9h) reset value = 0000 0000b sbuf - serial buffer register for uart (99h) reset value = xxxx xxxxb baud rates f osc = 16.384 mhz f osc = 24 mhz brl error (%) brl error (%) 115200 247 1.23 243 0.16 57600 238 1.23 230 0.16 38400 229 1.23 217 0.16 28800 220 1.23 204 0.16 19200 203 0.63 178 0.16 9600 149 0.31 100 0.16 4800 43 1.23 - - baud rates f osc = 16.384 mhz f osc = 24 mhz brl error (%) brl error (%) 4800 247 1.23 243 0.16 2400 238 1.23 230 0.16 1200 220 1.23 202 3.55 600 185 0.16 152 0.16 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ?
56 7683c?usb?11/07 at83c5134/35/36 brl - baud rate reload register for the internal ba ud rate generator, uart (9ah) reset value = 0000 0000b table 14-2. t2con register t2con - timer 2 control register (c8h) reset value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# bit number bit mnemonic description 7 tf2 timer 2 overflow flag must be cleared by software. set by hardware on timer 2 overflow, if rclk = 0 an d tclk = 0. 6 exf2 timer 2 external flag set when a capture or a reload is caused by a negat ive transition on t2ex pin if exen2 = 1. when set, causes the cpu to vector to timer 2 inter rupt routine when timer 2 interrupt is enabled. must be cleared by software. exf2 doesn?t cause an interrupt in up/down counter mode (dcen = 1) 5 rclk receive clock bit for uart cleared to use timer 1 overflow as receive clock fo r serial port in mode 1 or 3. set to use timer 2 overflow as receive clock for se rial port in mode 1 or 3. 4 tclk transmit clock bit for uart cleared to use timer 1 overflow as transmit clock f or serial port in mode 1 or 3. set to use timer 2 overflow as transmit clock for s erial port in mode 1 or 3. 3 exen2 timer 2 external enable bit cleared to ignore events on t2ex pin for timer 2 op eration. set to cause a capture or reload when a negative tr ansition on t2ex pin is detected, if timer 2 is not used to clock the serial port. 2 tr2 timer 2 run control bit cleared to turn off timer 2. set to turn on timer 2. 1 c/t2# timer/counter 2 select bit cleared for timer operation (input from internal cl ock system: f clk periph ). set for counter operation (input from t2 input pin, falling edge trigger). must be 0 for clock out mode. 0 cp/rl2# timer 2 capture/reload bit if rclk = 1 or tclk = 1, cp/rl2# is ignored and tim er is forced to auto-reload on timer 2 overflow. cleared to auto-reload on timer 2 overflows or nega tive transitions on t2ex pin if exen2 = 1. set to capture on negative transitions on t2ex pin if exen2 = 1.
57 7683c?usb?11/07 at83c5134/35/36 table 14-3. pcon register pcon - power control register (87h) reset value = 00x1 0000b not bit addressable power-off flag reset value will be 1 only after a p ower on (cold reset). a warm reset doesn?t affect the value of this bit. 7 6 5 4 3 2 1 0 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7 smod1 serial port mode bit 1 for uart set to select double baud rate in mode 1, 2 or 3. 6 smod0 serial port mode bit 0 for uart cleared to select sm0 bit in scon register. set to select fe bit in scon register. 5 - reserved the value read from this bit is indeterminate. do n ot set this bit. 4 pof power-off flag cleared to recognize next reset type. set by hardware when v cc rises from 0 to its nominal voltage. can also be s et by software. 3 gf1 general-purpose flag cleared by user for general-purpose usage. set by user for general-purpose usage. 2 gf0 general-purpose flag cleared by user for general-purpose usage. set by user for general-purpose usage. 1 pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0 idl idle mode bit cleared by hardware when interrupt or reset occurs. set to enter idle mode.
58 7683c?usb?11/07 at83c5134/35/36 table 14-4. bdrcon register bdrcon - baud rate control register (9bh) reset value = xxx0 0000b not bit addressable 7 6 5 4 3 2 1 0 - - - brr tbck rbck spd src bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do n ot set this bit 6 - reserved the value read from this bit is indeterminate. do n ot set this bit 5 - reserved the value read from this bit is indeterminate. do n ot set this bit. 4 brr baud rate run control bit cleared to stop the internal baud rate generator. set to start the internal baud rate generator. 3 tbck transmission baud rate generator selection bit for uart cleared to select timer 1 or timer 2 for the baud r ate generator. set to select internal baud rate generator. 2 rbck reception baud rate generator selection bit for uart cleared to select timer 1 or timer 2 for the baud r ate generator. set to select internal baud rate generator. 1 spd baud rate speed control bit for uart cleared to select the slow baud rate generator. set to select the fast baud rate generator. 0 src baud rate source select bit in mode 0 for uart cleared to select f osc /12 as the baud rate generator (f clk periph /6 in x2 mode). set to select the internal baud rate generator for uarts in mode 0.
59 7683c?usb?11/07 at83c5134/35/36 15. dual data pointer register the additional data pointer can be used to speed up code execution and reduce code size. the dual dptr structure is a way by which the chip will specify the address of an external data memory location. there are two 16-bit dptr register s that address the external memory, and a single bit called dps = auxr1.0 (see table 15-1) tha t allows the program code to switch between them (see figure 15-1). figure 15-1. use of dual pointer table 15-1. auxr1 register auxr1- auxiliary register 1(0a2h) reset value = xxxx x0x0b not bit addressable a. bit 2 stuck at 0; this allows to use inc auxr1 t o toggle dps without changing gf3. assembly language external data memory auxr1(a2h) dps dph(83h) dpl(82h) 0 7 dptr0 dptr1 7 6 5 4 3 2 1 0 - - - - gf3 0 - dps bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do n ot set this bit. 6 - reserved the value read from this bit is indeterminate. do n ot set this bit. 5 - reserved the value read from this bit is indeterminate. do n ot set this bit. 4 - reserved the value read from this bit is indeterminate. do n ot set this bit. 3 gf3 this bit is a general-purpose user flag. 2 0 always cleared. 1 - reserved the value read from this bit is indeterminate. do n ot set this bit. 0 dps data pointer selection cleared to select dptr0. set to select dptr1.
60 7683c?usb?11/07 at83c5134/35/36 ; block move using dual data pointers ; modifies dptr0, dptr1, a and psw ; note: dps exits opposite of entry state ; unless an extra inc auxr1 is added ; 00a2 auxr1 equ 0a2h ; 0000 909000mov dptr,#source ; address of source 0003 05a2 inc auxr1 ; switch data pointers 0005 90a000 mov dptr,#dest ; address of dest 0008 loop: 0008 05a2 inc auxr1 ; switch data pointers 000a e0 movx a,@dptr ; get a byte from source 000b a3 inc dptr ; increment source address 000c 05a2 inc auxr1 ; switch data pointers 000e f0 movx @dptr,a ; write the byte to dest 000f a3 inc dptr ; increment dest address 0010 70f6jnz loop ; check for 0 terminator 0012 05a2 inc auxr1 ; (optional) restore dps inc is a short (2 bytes) and fast (12 clocks) way t o manipulate the dps bit in the auxr1 sfr. however, note that the inc instruction does not dir ectly force the dps bit to a particular state, but simply toggles it. in simple routines, such as the block move example, only the fact that dps is toggled in the proper sequence matters, not its actual value. in other words, the block move routine works the same whether dps is '0' or '1' on entry. observe that without the last instruc- tion (inc auxr1), the routine will exit with dps in the opposite state.
61 7683c?usb?11/07 at83c5134/35/36 16. interrupt system 16.1 overview the at83c5134/35/36 has a total of 11 interrupt vec tors: two external interrupts (int0 and int1 ), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, spi interrupt, keyboard interrupt, usb interrupt and the pca global interru pt. these interrupts are shown in figure 16-1. figure 16-1. interrupt control system each of the interrupt sources can be individually e nabled or disabled by setting or clearing a bit in the interrupt enable register ( table 16-2 ). this register also contains a global disable bit , which must be cleared to disable all interrupts at once. each interrupt source can also be individually prog rammed to one out of four priority levels by setting or clearing a bit in the interrupt priority register (table 16-3.) and in the interrupt priori ty ie1 0 3 high priority interrupt interrupt polling sequence, decreasing from high-to-low priority low priority interrupt global disable individual enable exf2 tf2 ti ri tf0 int0 int1 tf1 iph, ipl ie0 0 3 0 3 0 3 0 3 0 3 0 3 pca it kbd it spi it 0 3 0 3 0 3 uepint usbint 0 3 twi it 1 1 0 0 it0 tcon.0 it1 tcon.2
62 7683c?usb?11/07 at83c5134/35/36 high register ( table 16-4 ). table 16-1. shows the bit values and priority le vels associated with each combination. 16.2 registers the pca interrupt vector is located at address 0033 h, the spi interrupt vector is located at address 004bh and keyboard interrupt vector is loca ted at address 003bh. all other vectors addresses are the same as standard c52 devices. table 16-1. priority level bit values a low-priority interrupt can be interrupted by a hi gh priority interrupt, but not by another low-prior - ity interrupt. a high-priority interrupt can?t be i nterrupted by any other interrupt source. if two interrupt requests of different priority lev els are received simultaneously, the request of higher priority level is serviced. if interrupt req uests of the same priority level are received simul - taneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence. iph.x ipl.x interrupt level priority 0 0 0 (lowest) 0 1 1 1 0 2 1 1 3 (highest)
63 7683c?usb?11/07 at83c5134/35/36 table 16-2. ien0 register ien0 - interrupt enable register (a8h) reset value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 ea ec et2 es et1 ex1 et0 ex0 bit number bit mnemonic description 7 ea enable all interrupt bit cleared to disable all interrupts. set to enable all interrupts. 6 ec pca interrupt enable bit cleared to disable. set to enable. 5 et2 timer 2 overflow interrupt enable bit cleared to disable timer 2 overflow interrupt. set to enable timer 2 overflow interrupt. 4 es serial port enable bit cleared to disable serial port interrupt. set to enable serial port interrupt. 3 et1 timer 1 overflow interrupt enable bit cleared to disable timer 1 overflow interrupt. set to enable timer 1 overflow interrupt. 2 ex1 external interrupt 1 enable bit cleared to disable external interrupt 1. set to enable external interrupt 1. 1 et0 timer 0 overflow interrupt enable bit cleared to disable timer 0 overflow interrupt. set to enable timer 0 overflow interrupt. 0 ex0 external interrupt 0 enable bit cleared to disable external interrupt 0. set to enable external interrupt 0.
64 7683c?usb?11/07 at83c5134/35/36 table 16-3. ipl0 register ipl0 - interrupt priority register (b8h) reset value = x000 0000b bit addressable 7 6 5 4 3 2 1 0 - ppcl pt2l psl pt1l px1l pt0l px0l bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do n ot set this bit. 6 ppcl pca interrupt priority bit refer to ppch for priority level. 5 pt2l timer 2 overflow interrupt priority bit refer to pt2h for priority level. 4 psl serial port priority bit refer to psh for priority level. 3 pt1l timer 1 overflow interrupt priority bit refer to pt1h for priority level. 2 px1l external interrupt 1 priority bit refer to px1h for priority level. 1 pt0l timer 0 overflow interrupt priority bit refer to pt0h for priority level. 0 px0l external interrupt 0 priority bit refer to px0h for priority level.
65 7683c?usb?11/07 at83c5134/35/36 table 16-4. iph0 register iph0 - interrupt priority high register (b7h) reset value = x000 0000b not bit addressable 7 6 5 4 3 2 1 0 - ppch pt2h psh pt1h px1h pt0h px0h bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do n ot set this bit. 6 ppch pca interrupt priority high bit. ppch ppcl priority level 0 0 lowest 0 1 1 0 1 1 highest 5 pt2h timer 2 overflow interrupt priority high bit pt2h pt2l priority level 0 0 lowest 0 1 1 0 1 1 highest 4 psh serial port priority high bit psh psl priority level 0 0 lowest 0 1 1 0 1 1 highest 3 pt1h timer 1 overflow interrupt priority high bit pt1h pt1l priority level 0 0 lowest 0 1 1 0 1 1 highest 2 px1h external interrupt 1 priority high bit px1h px1l priority level 0 0 lowest 0 1 1 0 1 1 highest 1 pt0h timer 0 overflow interrupt priority high bit pt0h pt0l priority level 0 0 lowest 0 1 1 0 1 1 highest 0 px0h external interrupt 0 priority high bit px0h px0l priority level 0 0 lowest 0 1 1 0 1 1 highest
66 7683c?usb?11/07 at83c5134/35/36 table 16-5. ien1 register ien1 - interrupt enable register (b1h) reset value = x0xx x000b not bit addressable 7 6 5 4 3 2 1 0 - eusb - - - espi etwi ekb bit number bit mnemonic description 7 - reserved 6 eusb usb interrupt enable bit cleared to disable usb interrupt. set to enable usb interrupt. 5 - reserved 4 - reserved 3 - reserved 2 espi spi interrupt enable bit cleared to disable spi interrupt. set to enable spi interrupt. 1 etwi twi interrupt enable bit cleared to disable twi interrupt. set to enable twi interrupt. 0 ekb keyboard interrupt enable bit cleared to disable keyboard interrupt. set to enable keyboard interrupt.
67 7683c?usb?11/07 at83c5134/35/36 table 16-6. ipl1 register ipl1 - interrupt priority register (b2h) reset value = x0xx x000b not bit addressable 7 6 5 4 3 2 1 0 - pusbl - - - pspil ptwil pkbdl bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do n ot set this bit. 6 pusbl usb interrupt priority bit refer to pusbh for priority level. 5 - reserved the value read from this bit is indeterminate. do n ot set this bit. 4 - reserved the value read from this bit is indeterminate. do n ot set this bit. 3 - reserved the value read from this bit is indeterminate. do n ot set this bit. 2 pspil spi interrupt priority bit refer to pspih for priority level. 1 ptwil twi interrupt priority bit refer to ptwih for priority level. 0 pkbl keyboard interrupt priority bit refer to pkbh for priority level.
68 7683c?usb?11/07 at83c5134/35/36 table 16-7. iph1 register iph1 - interrupt priority high register (b3h) reset value = x0xx x000b not bit addressable 7 6 5 4 3 2 1 0 - pusbh - - - pspih ptwih pkbh bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do n ot set this bit. 6 pusbh usb interrupt priority high bit pusbh pusbl priority level 0 0 lowest 0 1 1 0 1 1 highest 5 - reserved the value read from this bit is indeterminate. do n ot set this bit. 4 - reserved the value read from this bit is indeterminate. do n ot set this bit. 3 - reserved the value read from this bit is indeterminate. do n ot set this bit. 2 pspih spi interrupt priority high bit pspih pspil priority level 0 0 lowest 0 1 1 0 1 1 highest 1 ptwih twi interrupt priority high bit ptwih ptwil priority level 0 0 lowest 0 1 1 0 1 1 highest 0 pkbh keyboard interrupt priority high bit pkbh pkbl priority level 0 0 lowest 0 1 1 0 1 1 highest
69 7683c?usb?11/07 at83c5134/35/36 16.3 interrupt sources and vector addresses table 16-8. vector table number polling priority interrupt source interrupt request vector address 0 0 reset 0000h 1 1 int0 ie0 0003h 2 2 timer 0 tf0 000bh 3 3 int1 ie1 0013h 4 4 timer 1 if1 001bh 5 6 uart ri+ti 0023h 6 7 timer 2 tf2+exf2 002bh 7 5 pca cf + ccfn (n = 0-4) 0033h 8 8 keyboard kbdit 003bh 9 9 twi twiit 0043h 10 10 spi spiit 004bh 11 11 0053h 12 12 005bh 13 13 0063h 14 14 usb uepint + usbint 006bh 15 15 0073h
70 7683c?usb?11/07 at83c5134/35/36 17. keyboard interface 17.1 introduction the at83c5134/35/36 implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. it is based on 8 inputs with progr ammable interrupt capability on both high or low level. these inputs are available as an alterna te function of p1 and allow to exit from idle and power down modes. 17.2 description the keyboard interface communicates with the c51 co re through 3 special function registers: kbls, the keyboard level selection register (table 1 7-3), kbe, the keyboard interrupt enable register (table 17-2), and kbf, the keyboard flag re gister (table 17-1). 17.2.1 interrupt the keyboard inputs are considered as 8 independent interrupt sources sharing the same inter- rupt vector. an interrupt enable bit (kbd in ie1) a llows global enable or disable of the keyboard interrupt (see figure 17-1). as detailed in figure 17 -2 each keyboard input has the capability to detect a programmable level according to kbls.x bit value. level detection is then reported in interrupt flags kbf.x that can be masked by softwar e using kbe.x bits. this structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage of p1 inputs for other purpose. figure 17-1. keyboard interface block diagram figure 17-2. keyboard input circuitry p1.0 keyboard interface interrupt request kbd ie1.0 input circuitry p1.1 input circuitry p1.2 input circuitry p1.3 input circuitry p1.4 input circuitry p1.5 input circuitry p1.6 input circuitry p1.7 input circuitry kbdit p1:x kbe.x kbf.x kbls.x 01 vcc internal pull-up
71 7683c?usb?11/07 at83c5134/35/36 17.2.2 power reduction mode p1 inputs allow exit from idle and power down modes as detailed in section ?power-down mode?. 17.3 registers table 17-1. kbf register kbf - keyboard flag register (9eh) reset value = 0000 0000b 7 6 5 4 3 2 1 0 kbf7 kbf6 kbf5 kbf4 kbf3 kbf2 kbf1 kbf0 bit number bit mnemonic description 7 kbf7 keyboard line 7 flag set by hardware when the port line 7 detects a prog rammed level. it generates a keyboard interrupt request if the kbkbie.7 bit in k bie register is set. cleared by hardware when reading kbf sfr by softwar e. 6 kbf6 keyboard line 6 flag set by hardware when the port line 6 detects a prog rammed level. it generates a keyboard interrupt request if the kbie.6 bit in kbi e register is set. cleared by hardware when reading kbf sfr by softwar e. 5 kbf5 keyboard line 5 flag set by hardware when the port line 5 detects a prog rammed level. it generates a keyboard interrupt request if the kbie.5 bit in kbi e register is set. cleared by hardware when reading kbf sfr by softwar e. 4 kbf4 keyboard line 4 flag set by hardware when the port line 4 detects a prog rammed level. it generates a keyboard interrupt request if the kbie.4 bit in kbi e register is set. cleared by hardware when reading kbf sfr by softwar e. 3 kbf3 keyboard line 3 flag set by hardware when the port line 3 detects a prog rammed level. it generates a keyboard interrupt request if the kbie.3 bit in kbi e register is set. cleared by hardware when reading kbf sfr by softwar e. 2 kbf2 keyboard line 2 flag set by hardware when the port line 2 detects a prog rammed level. it generates a keyboard interrupt request if the kbie.2 bit in kbi e register is set. must be cleared by software. 1 kbf1 keyboard line 1 flag set by hardware when the port line 1 detects a prog rammed level. it generates a keyboard interrupt request if the kbie.1 bit in kbi e register is set. cleared by hardware when reading kbf sfr by softwar e. 0 kbf0 keyboard line 0 flag set by hardware when the port line 0 detects a prog rammed level. it generates a keyboard interrupt request if the kbie.0 bit in kbi e register is set. cleared by hardware when reading kbf sfr by softwar e.
72 7683c?usb?11/07 at83c5134/35/36 table 17-2. kbe register kbe - keyboard input enable register (9dh) reset value = 0000 0000b 7 6 5 4 3 2 1 0 kbe7 kbe6 kbe5 kbe4 kbe3 kbe2 kbe1 kbe0 bit number bit mnemonic description 7 kbe7 keyboard line 7 enable bit cleared to enable standard i/o pin. set to enable kbf.7 bit in kbf register to generate an interrupt request. 6 kbe6 keyboard line 6 enable bit cleared to enable standard i/o pin. set to enable kbf.6 bit in kbf register to generate an interrupt request. 5 kbe5 keyboard line 5 enable bit cleared to enable standard i/o pin. set to enable kbf.5 bit in kbf register to generate an interrupt request. 4 kbe4 keyboard line 4 enable bit cleared to enable standard i/o pin. set to enable kbf.4 bit in kbf register to generate an interrupt request. 3 kbe3 keyboard line 3 enable bit cleared to enable standard i/o pin. set to enable kbf.3 bit in kbf register to generate an interrupt request. 2 kbe2 keyboard line 2 enable bit cleared to enable standard i/o pin. set to enable kbf.2 bit in kbf register to generate an interrupt request. 1 kbe1 keyboard line 1 enable bit cleared to enable standard i/o pin. set to enable kbf.1 bit in kbf register to generate an interrupt request. 0 kbe0 keyboard line 0 enable bit cleared to enable standard i/o pin. set to enable kbf.0 bit in kbf register to generate an interrupt request.
73 7683c?usb?11/07 at83c5134/35/36 table 17-3. kbls register kbls- keyboard level selector register (9ch) reset value = 0000 0000b 7 6 5 4 3 2 1 0 kbls7 kbls6 kbls5 kbls4 kbls3 kbls2 kbls1 kbls0 bit number bit mnemonic description 7 kbls7 keyboard line 7 level selection bit cleared to enable a low level detection on port lin e 7. set to enable a high level detection on port line 7 . 6 kbls6 keyboard line 6 level selection bit cleared to enable a low level detection on port lin e 6. set to enable a high level detection on port line 6 . 5 kbls5 keyboard line 5 level selection bit cleared to enable a low level detection on port lin e 5. set to enable a high level detection on port line 5 . 4 kbls4 keyboard line 4 level selection bit cleared to enable a low level detection on port lin e 4. set to enable a high level detection on port line 4 . 3 kbls3 keyboard line 3 level selection bit cleared to enable a low level detection on port lin e 3. set to enable a high level detection on port line 3 . 2 kbls2 keyboard line 2 level selection bit cleared to enable a low level detection on port lin e 2. set to enable a high level detection on port line 2 . 1 kbls1 keyboard line 1 level selection bit cleared to enable a low level detection on port lin e 1. set to enable a high level detection on port line 1 . 0 kbls0 keyboard line 0 level selection bit cleared to enable a low level detection on port lin e 0. set to enable a high level detection on port line 0 .
74 7683c?usb?11/07 at83c5134/35/36 18. programmable led at83c5134/35/36 have up to 4 programmable led curre nt sources, configured by the register ledcon. reset value = 00h table 18-1. ledcon register ledcon (s:f1h) led control register 7 6 5 4 3 2 1 0 led3 led2 led1 led0 bit number bit mnemonic description 7:6 led3 port led3 configuration 0 0 standard c51 port 0 1 2 ma current source when p3.7 is low 1 0 4 ma current source when p3.7 is low 1 1 10 ma current source when p3.7 is low 5:4 led2 port /led2 configuration 0 0 standard c51 port 0 1 2 ma current source when p3.6 is low 1 0 4 ma current source when p3.6 is low 1 1 10 ma current source when p3.6 is low 3:2 led1 port/ led1 configuration 0 0 standard c51 port 0 1 2 ma current source when p3.5 is low 1 0 4 ma current source when p3.5 is low 1 1 10 ma current source when p3.5 is low 1:0 led0 port/ led0 configuration 0 0 standard c51 port 0 1 2 ma current source when p3.3 is low 1 0 4 ma current source when p3.3 is low 1 1 10 ma current source when p3.3 is low
75 7683c?usb?11/07 at83c5134/35/36 19. serial peripheral interface (spi) the serial peripheral interface module (spi) allows full-duplex, synchronous, serial communica- tion between the mcu and peripheral devices, includ ing other mcus. 19.1 features features of the spi module include the following: ? full-duplex, three-wire synchronous transfers ? master or slave operation ? eight programmable master clock rates ? serial clock with programmable polarity and phase ? master mode fault error flag with mcu interrupt ca pability ? write collision flag protection 19.2 signal description figure 19-1 shows a typical spi bus configuration using one ma ster controller and many slave peripherals. the bus is made of three wires connect ing all the devices: figure 19-1. spi master/slaves interconnection the master device selects the individual slave devi ces by using four pins of a parallel port to control the four ss pins of the slave devices. 19.2.1 master output slave input (mosi) this 1-bit signal is directly connected between the master device and a slave device. the mosi line is used to transfer data in series from the ma ster to the slave. therefore, it is an output sig- nal from the master, and an input signal to a slave . a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb) last. 19.2.2 master input slave output (miso) this 1-bit signal is directly connected between the slave device and a master device. the miso line is used to transfer data in series from the sl ave to the master. therefore, it is an output sig- nal from the slave, and an input signal to the mast er. a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb) last. slave 1 miso mosi sck ss miso mosi sck ss port 01 2 3 slave 3 miso mosi sck ss slave 4 miso mosi sck ss slave 2 miso mosi sck ss vdd master
76 7683c?usb?11/07 at83c5134/35/36 19.2.3 spi serial clock (sck) this signal is used to synchronize the data movemen t both in and out the devices through their mosi and miso lines. it is driven by the master for eight clock cycles which allows to exchange one byte on the serial lines. 19.2.4 slave select (ss ) each slave peripheral is selected by one slave sele ct pin (ss ). this signal must stay low for any message for a slave. it is obvious that only one ma ster (ss high level) can drive the network. the master may select each slave device by software through port pins ( figure 19-1 ). to pre- vent bus conflicts on the miso line, only one slave should be selected at a time by the master for a transmission. in a master configuration, the ss line can be used in conjunction with the modf flag in the spi status register (spsta) to prevent multiple masters from driving mosi and sck (see section ?error conditions?, page 79). a high level on the ss pin puts the miso line of a slave spi in a high-im pedance state. the ss pin could be used as a general-purpose if the foll owing conditions are met: ? the device is configured as a master and the ssdis control bit in spcon is set. this kind of configuration can be found when only one master is driving the network and there is no way that the ss pin could be pulled low. therefore, the modf flag in the spsta will never be set (1) . ? the device is configured as a slave with cpha and ssdis control bits set (2) this kind of configuration can happen when the system comprises one master and one slave only. therefore, the device should always be selected and there is no reason that the master uses the ss pin to select the communicating slave device. notes: 1. clearing ssdis control bit does not clear m odf. 2. special care should be taken not to set ssdis con trol bit when cpha =?0? because in this mode, the ss is used to start the transmission. 19.2.5 baud rate in master mode, the baud rate can be selected from a baud rate generator which is controlled by three bits in the spcon register: spr2, spr1 and sp r0. the master clock is chosen from one of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128. table 19-1 gives the different clock rates selected by spr2:s pr1:spr0: table 19-1. spi master baud rate selection spr2 spr1 spr0 clock rate baud rate divisor (bd) 0 0 0 don?t use no brg 0 0 1 f clk periph /4 4 0 1 0 f clk periph /8 8 0 1 1 f clk periph /16 16 1 0 0 f clk periph /32 32 1 0 1 f clk periph /64 64 1 1 0 f clk periph /128 128 1 1 1 don?t use no brg
77 7683c?usb?11/07 at83c5134/35/36 19.3 functional description figure 19-2 shows a detailed structure of the spi module. figure 19-2. spi module block diagram 19.3.1 operating modes the serial peripheral interface can be configured a s one of the two modes: master mode or slave mode. the configuration and initialization of the spi module is made through one register: ? the serial peripheral control register (spcon) once the spi is configured, the data exchange is ma de using: ? spcon ? the serial peripheral status register (spsta) ? the serial peripheral data register (spdat) during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (sck) synchronizes shifting and sampling on the two serial data lines (mosi and miso). a slave sele ct line (ss ) allows individual selection of a slave spi device; slave devices that are not select ed do not interfere with spi bus activities. when the master device transmits data to the slave device via the mosi line, the slave device responds by sending data to the master device via t he miso line. this implies full-duplex trans- mission with both data out and data in synchronized with the same clock (figure 19-3). shift register 0 1 2 3 4 5 6 7 internal bus pin control logic miso mosi sck m s clock logic clock divider clock select /4 /64 /128 spi interrupt request 8-bit bus 1-bit signal ss fclk periph /32 /8 /16 receive data register spdat spi control spsta cpha spr0 spr1 cpol mstr ssdis spen spr2 spcon wcol modf spif - - - - sserr
78 7683c?usb?11/07 at83c5134/35/36 figure 19-3. full-duplex master/slave interconnection 19.3.1.1 master mode the spi operates in master mode when the master bit , mstr (1) , in the spcon register is set. only one master spi device can initiate transmissio ns. software begins the transmission from a master spi module by writing to the serial peripher al data register (spdat). if the shift register is empty, the byte is immediately transferred to th e shift register. the byte begins shifting out on mosi pin under the control of the serial clock, sck . simultaneously, another byte shifts in from the slave on the master?s miso pin. the transmissio n ends when the serial peripheral transfer data flag, spif, in spsta becomes set. at the same time that spif becomes set, the received byte from the slave is transferred to the receive d ata register in spdat. software clears spif by reading the serial peripheral status register (s psta) with the spif bit set, and then reading the spdat. 19.3.1.2 slave mode the spi operates in slave mode when the master bit, mstr (2) , in the spcon register is cleared. before a data transmission occurs, the sla ve select pin, ss , of the slave device must be set to?0?. ss must remain low until the transmission is complete . in a slave spi module, data enters the shift regist er under the control of the sck from the mas- ter spi module. after a byte enters the shift regis ter, it is immediately transferred to the receive data register in spdat, and the spif bit is set. to prevent an overflow condition, slave software must then read the spdat before another byte enters the shift register (3) . a slave spi must complete the write to the spdat (shift register) at least one bus cycle before the master spi starts a transmission. if the write to the data reg ister is late, the spi transmits the data already i n the shift register from the previous transmission. 19.3.2 transmission formats software can select any of four combinations of ser ial clock (sck) phase and polarity using two bits in the spcon: the clock polarity (cpol (4) ) and the clock phase (cpha 4 ). cpol defines the default sck line level in idle state. it has no significant effect on the transmission format. cpha defines the edges on which the input data are sampled and the edges on which the out- put data are shifted (figure 19-4 and figure 19-5). t he clock phase and polarity should be identical for the master spi device and the communi cating slave device. 8-bit shift register spi clock generator master mcu 8-bit shift register miso miso mosi mosi sck sck vss vdd ss ss slave mcu 1. the spi module should be configured as a master b efore it is enabled (spen set). also the mas- ter spi should be configured before the slave spi. 2. the spi module should be configured as a slave be fore it is enabled (spen set). 3. the maximum frequency of the sck for an spi confi gured as a slave is the bus clock speed. 4. before writing to the cpol and cpha bits, the spi should be disabled (spen =?0?).
79 7683c?usb?11/07 at83c5134/35/36 figure 19-4. data transmission format (cpha = 0) figure 19-5. data transmission format (cpha = 1) figure 19-6. cpha/ss timing as shown in figure 19-5 , the first sck edge is the msb capture strobe. the refore the slave must begin driving its data before the first sck ed ge, and a falling edge on the ss pin is used to start the transmission. the ss pin must be toggled high and then low between each byte trans- mitted (figure 19-2). figure 19-6 shows an spi transmission in which cpha is?1?. in this case, the master begins driv- ing its mosi pin on the first sck edge. therefore t he slave uses the first sck edge as a start transmission signal. the ss pin can remain low between transmissions ( figure 19-1 ). this for- mat may be preferable in systems having only one ma ster and only one slave driving the miso data line. 19.3.3 error conditions the following flags in the spsta signal spi error c onditions: msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 1 3 2 4 5 6 7 8 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 1 3 2 4 5 6 7 8 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number byte 1 byte 2 byte 3 miso/mosi master ss slave ss (cpha = 1) slave ss (cpha = 0)
80 7683c?usb?11/07 at83c5134/35/36 19.3.3.1 mode fault (modf) mode fault error in master mode spi indicates that the level on the slave select (ss ) pin is inconsistent with the actual mode of the device. mo df is set to warn that there may have a multi-master conflict for system control. in this c ase, the spi system is affected in the following ways: ? an spi receiver/error cpu interrupt request is gen erated, ? the spen bit in spcon is cleared. this disable the spi, ? the mstr bit in spcon is cleared when ss disable (ssdis) bit in the spcon register is clear ed, the modf flag is set when the ss signal becomes ?0?. however, as stated before, for a system with one ma ster, if the ss pin of the master device is pulled low, there is no way that another master att empt to drive the network. in this case, to pre- vent the modf flag from being set, software can set the ssdis bit in the spcon register and therefore making the ss pin as a general-purpose i/o pin. clearing the modf bit is accomplished by a read of spsta register with modf bit set, followed by a write to the spcon register. spen control bit may be restored to its original set state after the modf bit has been cleared. 19.3.3.2 write collision (wcol) a write collision (wcol) flag in the spsta is set w hen a write to the spdat register is done during a transmit sequence. wcol does not cause an interruption, and the transf er continues uninterrupted. clearing the wcol bit is done through a software se quence of an access to spsta and an access to spdat. 19.3.3.3 overrun condition an overrun condition occurs when the master device tries to send several data bytes and the slave devise has not cleared the spif bit issuing f rom the previous data byte transmitted. in this case, the receiver buffer contains the byte sent af ter the spif bit was last cleared. a read of the spdat returns this byte. all others bytes are lost. this condition is not detected by the spi periphera l. 19.3.4 interrupts two spi status flags can generate a cpu interrupt r equests: table 19-2. spi interrupts serial peripheral data transfer flag, spif: this bi t is set by hardware when a transfer has been completed. spif bit generates transmitter cpu inter rupt requests. flag request spif (sp data transfer) spi transmitter interrupt re quest modf (mode fault) spi receiver/error interrupt request (if ssdis = ?0 ?)
81 7683c?usb?11/07 at83c5134/35/36 mode fault flag, modf: this bit becomes set to indi cate that the level on the ss is inconsistent with the mode of the spi. modf with ssdis reset, ge nerates receiver/error cpu interrupt requests. figure 19-7 gives a logical view of the above statem ents. figure 19-7. spi interrupt requests generation 19.3.5 registers there are three registers in the module that provid e control, status and data storage functions. these registers are describes in the following paragraphs. 19.3.5.1 serial peripheral control register (spcon) ? the serial peripheral control register does the fo llowing: ? selects one of the master clock rates ? configure the spi module as master or slave ? selects serial clock polarity and phase ? enables the spi module ? frees the ss pin for a general-purpose table 19-3 describes this register and explains the use of each bit. ssdis modf cpu interrupt request spi receiver/error cpu interrupt request spi transmitter spi cpu interrupt request spif table 19-3. spcon register 7 6 5 4 3 2 1 0 spr2 spen ssdis mstr cpol cpha spr1 spr0 bit number bit mnemonic description 7 spr2 serial peripheral rate 2 bit with spr1 and spr0 define the clock rate. 6 spen serial peripheral enable cleared to disable the spi interface. set to enable the spi interface. 5 ssdis ss disable cleared to enable ss in both master and slave modes. set to disable ss in both master and slave modes. in slave mode, thi s bit has no effect if cpha = ?0?. 5 mstr serial peripheral master cleared to configure the spi as a slave. set to configure the spi as a master. 4 cpol clock polarity cleared to have the sck set to ?0? in idle state. set to have the sck set to ?1? in idle state.
82 7683c?usb?11/07 at83c5134/35/36 reset value = 0001 0100b not bit addressable 19.3.5.2 serial peripheral status register (spsta) the serial peripheral status register contains flag s to signal the following conditions: ? data transfer complete ? write collision ? inconsistent logic level on ss pin (mode fault error) table 19-4 describes the spsta register and explains the use of every bit in the register. table 19-4. spsta register spsta - serial peripheral status and control regist er (0c4h) 3 cpha clock phase cleared to have the data sampled when the sck leave s the idle state (see cpol). set to have the data sampled when the sck returns t o idle state (see cpol). 2 spr1 spr2 spr1 spr0 serial peripheral rate 0 0 0 reserved 0 0 1 f clk periph/ 4 0 1 0 f clk periph/ 8 0 1 1 f clk periph/ 16 1 0 0 f clk periph/ 32 1 0 1 f clk periph/ 64 1 1 0 f clk periph/ 128 1 1 1 reserved 1 spr0 bit number bit mnemonic description table 3. 7 6 5 4 3 2 1 0 spif wcol sserr modf - - - - bit number bit mnemonic description 7 spif serial peripheral data transfer flag cleared by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. set by hardware to indicate that the data transfer has been completed. 6 wcol write collision flag cleared by hardware to indicate that no collision h as occurred or has been approved by a clearing sequence. set by hardware to indicate that a collision has be en detected. 5 sserr synchronous serial slave error flag set by hardware when ss is de- asserted before the end of a received data. cleared by disabling the spi (clearing spen bit in spcon).
83 7683c?usb?11/07 at83c5134/35/36 reset value = 00x0 xxxxb not bit addressable 19.3.5.3 serial peripheral data register (spdat) the serial peripheral data register ( table 19-5 ) is a read/write buffer for the receive data regis - ter. a write to spdat places data directly into the shift register. no transmit buffer is available in this model. a read of the spdat returns the value located in th e receive buffer and not the content of the shift register. table 19-5. spdat register spdat - serial peripheral data register (0c5h) reset value = indeterminate r7:r0: receive data bits spcon, spsta and spdat registers may be read and wr itten at any time while there is no on- going exchange. however, special care should be tak en when writing to them while a transmis- sion is on-going: ? do not change spr2, spr1 and spr0 ? do not change cpha and cpol ? do not change mstr ? clearing spen would immediately disable the periph eral ? writing to the spdat will cause an overflow 4 modf mode fault cleared by hardware to indicate that the ss pin is at appropriate logic level, or has been approved by a clearing sequence. set by hardware to indicate that the ss pin is at inappropriate logic level. 3 - reserved the value read from this bit is indeterminate. do n ot set this bit 2 - reserved the value read from this bit is indeterminate. do n ot set this bit 1 - reserved the value read from this bit is indeterminate. do n ot set this bit. 0 - reserved the value read from this bit is indeterminate. do n ot set this bit. bit number bit mnemonic description 7 6 5 4 3 2 1 0 r7 r6 r5 r4 r3 r2 r1 r0
84 7683c?usb?11/07 at83c5134/35/36 20. two wire interface ( twi ) this section describes the 2-wire interface. the 2- wire bus is a bi-directional 2-wire serial com- munication standard. it is designed primarily for s imple but efficient integrated circuit (ic) control . the system is comprised of two lines, scl (serial c lock) and sda (serial data) that carry infor- mation between the ics connected to them. the seria l data transfer is limited to 100 kbit/s in standard mode. various communication configuration can be designed using this bus. figure 20-1 shows a typical 2-wire bus configuration. all the devices connected to the bus can be mas- ter and slave. figure 20-1. 2-wire bus configuration scl sda device2 device1 devicen device3 ...
85 7683c?usb?11/07 at83c5134/35/36 figure 20-2. block diagram address register comparator timing & control logic arbitration & sink logic serial clock generator shift register control register status register status decoder input filter output stage input filter output stage ack status bits 88 7 8 internal bus timer 1 overflow f clk periph /4 interrupt sda scl ssadr sscon ssdat sscs
86 7683c?usb?11/07 at83c5134/35/36 20.1 description the cpu interfaces to the 2-wire logic via the foll owing four 8-bit special function registers: the synchronous serial control register (sscon; table 20-10 ), the synchronous serial data regis- ter (ssdat; table 20-11 ), the synchronous serial control and status regist er (sscs; table 20- 12 ) and the synchronous serial address register (ssad r table 20-13 ). sscon is used to enable the twi interface, to progr am the bit rate (see table 20-3 ), to enable slave modes, to acknowledge or not a received data, to send a start or a stop condition on the 2-wire bus, and to acknowledge a serial interru pt. a hardware reset disables the twi module. sscs contains a status code which reflects the stat us of the 2-wire logic and the 2-wire bus. the three least significant bits are always zero. t he five most significant bits contains the status code. there are 26 possible status codes. when sscs contains f8h, no relevant state informa- tion is available and no serial interrupt is reques ted. a valid status code is available in sscs one machine cycle after si is set by hardware and is st ill present one machine cycle after si has been reset by software. to table 20-9. give the sta tus for the master modes and miscellaneous states. ssdat contains a byte of serial data to be transmit ted or a byte which has just been received. it is addressable while it is not in process of shifti ng a byte. this occurs when 2-wire logic is in a defined state and the serial interrupt flag is set. data in ssdat remains stable as long as si is set. while data is being shifted out, data on the b us is simultaneously shifted in; ssdat always contains the last byte present on the bus. ssadr may be loaded with the 7-bit slave address (7 most significant bits) to which the twi module will respond when programmed as a slave tran smitter or receiver. the lsb is used to enable general call address (00h) recognition. figure 20-3 shows how a data transfer is accomplished on the 2 -wire bus. figure 20-3. complete data transfer on 2-wire bus the four operating modes are: ? master transmitter ? master receiver ? slave transmitter ? slave receiver data transfer in each mode of operation is shown in table to table 20-9 and figure 20-4. to figure 20-7.. these figures contain the following a bbreviations: s : start condition sda scl s start condition msb 1 2 7 8 9 ack acknowledgement signal from receiver acknowledgement signal from receiver 1 2 3-8 9 ack stop condition p clock line held low while interrupts are serviced
87 7683c?usb?11/07 at83c5134/35/36 r : read bit (high level at sda) w : write bit (low level at sda) a: acknowledge bit (low level at sda) a : not acknowledge bit (high level at sda) data: 8-bit data byte p : stop condition in figure 20-4 to figure 20-7, circles are used to in dicate when the serial interrupt flag is set. the numbers in the circles show the status code hel d in sscs. at these points, a service routine must be executed to continue or complete the serial transfer. these service routines are not crit- ical since the serial transfer is suspended until t he serial interrupt flag is cleared by software. when the serial interrupt routine is entered, the s tatus code in sscs is used to branch to the appropriate service routine. for each status code, the required software action and details of the following serial transfer are given in table to tab le 20-9. 20.1.1 master transmitter mode in the master transmitter mode, a number of data by tes are transmitted to a slave receiver (figure 20-4). before the master transmitter mode ca n be entered, sscon must be initialised as follows: cr0, cr1 and cr2 define the internal serial bit rat e if external bit rate generator is not used. ssie must be set to enable twi. sta, sto and si mus t be cleared. the master transmitter mode may now be entered by s etting the sta bit. the 2-wire logic will now test the 2-wire bus and generate a start condit ion as soon as the bus becomes free. when a start condition is transmitted, the serial i nterrupt flag (si bit in sscon) is set, and the status code in sscs will be 08h. this status must b e used to vector to an interrupt routine that loads ssdat with the slave address and the data dir ection bit (sla+w). when the slave address and the direction bit have b een transmitted and an acknowledgement bit has been received, si is set again and a number of status code in sscs are possible. there are 18h, 20h or 38h for the master mode and also 68 h, 78h or b0h if the slave mode was enabled (aa=logic 1). the appropriate action to be taken for each of these status code is detailed in table . this scheme is repeated until a stop condition is transmitted. ssie, cr2, cr1 and cr0 are not affected by the seri al transfer and are referred to table 7 to table 11. after a repeated start condition (state 1 0h) the twi module may switch to the mas- ter receiver mode by loading ssdat with sla+r. 20.1.2 master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmitter (figure 20-5). the transfer is initialized as in the master transmitter mode. when the start condition has been transmitted, the interrupt routi ne must load ssdat with the 7-bit slave table 20-1. sscon initialization cr2 ssie sta sto si aa cr1 cr0 bit rate 1 0 0 0 x bit rate bit rate
88 7683c?usb?11/07 at83c5134/35/36 address and the data direction bit (sla+r). the ser ial interrupt flag si must then be cleared before the serial transfer can continue. when the slave address and the direction bit have b een transmitted and an acknowledgement bit has been received, the serial interrupt flag is set again and a number of status code in sscs are possible. there are 40h, 48h or 38h for the mas ter mode and also 68h, 78h or b0h if the slave mode was enabled (aa=logic 1). the appropriat e action to be taken for each of these sta- tus code is detailed in table . this scheme is repea ted until a stop condition is transmitted. ssie, cr2, cr1 and cr0 are not affected by the seri al transfer and are referred to table 7 to table 11. after a repeated start condition (state 1 0h) the twi module may switch to the mas- ter transmitter mode by loading ssdat with sla+w. 20.1.3 slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter (figure 20-6). to initiate the slave receiver mode, ssadr and sscon must be loaded as follows: the upper 7 bits are the address to which the twi m odule will respond when addressed by a master. if the lsb (gc) is set the twi module will respond to the general call address (00h); otherwise it ignores the general call address. cr0, cr1 and cr2 have no effect in the slave mode. ssie must be set to enable the twi. the aa bit must be set to enable the own slave address or the general call address acknowledge- ment. sta, sto and si must be cleared. when ssadr and sscon have been initialised, the twi module waits until it is addressed by its own slave address followed by the data directio n bit which must be at logic 0 (w) for the twi to operate in the slave receiver mode. after its ow n slave address and the w bit have been received, the serial interrupt flag is set and a va lid status code can be read from sscs. this sta- tus code is used to vector to an interrupt service routine.the appropriate action to be taken for each of these status code is detailed in table . the slave receiver mode may also be entered if arbitration is lost while twi is in the master mode (states 68h and 78h). if the aa bit is reset during a transfer, twi modul e will return a not acknowledge (logic 1) to sda after the next received data byte. while aa is rese t, the twi module does not respond to its own slave address. however, the 2-wire bus is still mon itored and address recognition may be resume at any time by setting aa. this means that t he aa bit may be used to temporarily isolate the module from the 2-wire bus. table 20-2. ssadr: slave receiver mode initialization a6 a5 a4 a3 a2 a1 a0 gc own slave address table 20-3. sscon: slave receiver mode initialization cr2 ssie sta sto si aa cr1 cr0 bit rate 1 0 0 0 1 bit rate bit rate
89 7683c?usb?11/07 at83c5134/35/36 20.1.4 slave transmitter mode in the slave transmitter mode, a number of data byt es are transmitted to a master receiver (figure 20-7). data transfer is initialized as in th e slave receiver mode. when ssadr and sscon have been initialized, the twi module waits u ntil it is addressed by its own slave address followed by the data direction bit which mu st be at logic 1 (r) for twi to operate in the slave transmitter mode. after its own slave address and the r bit have been received, the serial interrupt flag is set and a valid status code can b e read from sscs. this status code is used to vector to an interrupt service routine. the appropr iate action to be taken for each of these status code is detailed in table . the slave transmitter mo de may also be entered if arbitration is lost while the twi module is in the master mode. if the aa bit is reset during a transfer, the twi m odule will transmit the last byte of the transfer and enter state c0h or c8h. the twi module is switc hed to the not addressed slave mode and will ignore the master receiver if it continues the transfer. thus the master receiver receives all 1?s as serial data. while aa is reset, the twi modu le does not respond to its own slave address. however, the 2-wire bus is still monitored and addr ess recognition may be resume at any time by setting aa. this means that the aa bit may be us ed to temporarily isolate the twi module from the 2-wire bus. 20.1.5 miscellaneous states there are two sscs codes that do not correspond to a define twi hardware state (table 20-9 ). these codes are discuss hereafter. status f8h indicates that no relevant information i s available because the serial interrupt flag is not set yet. this occurs between other states and w hen the twi module is not involved in a serial transfer. status 00h indicates that a bus error has occurred during a twi serial transfer. a bus error is caused when a start or a stop condition occurs at a n illegal position in the format frame. examples of such illegal positions happen during th e serial transfer of an address byte, a data byte, or an acknowledge bit. when a bus error occur s, si is set. to recover from a bus error, the sto flag must be set and si must be cleared. this c auses the twi module to enter the not addressed slave mode and to clear the sto flag (no other bits in sscon are affected). the sda and scl lines are released and no stop conditio n is transmitted. 20.2 notes the twi module interfaces to the external 2-wire bu s via two port pins: scl (serial clock line) and sda (serial data line). to avoid low level asse rting on these lines when the twi module is enabled, the output latches of sda and slc must be set to logic 1. table 20-4. bit frequency configuration bit frequency ( khz) cr2 cr1 cr0 f osca = 12 mhz f osca = 16 mhz f osca divided by 0 0 0 47 62.5 256 0 0 1 53.5 71.5 224 0 1 0 62.5 83 192 0 1 1 75 100 160
90 7683c?usb?11/07 at83c5134/35/36 figure 20-4. format and state in the master transmitter mode 1 0 0 - - unused 1 0 1 100 133.3 120 1 1 0 200 266.6 60 1 1 1 0.5 <. < 62.5 0.67 <. < 83 timer 1 in mode 2 can be used as twi baudrate generator with the following formula: 96.(256-?timer1 reload value?) bit frequency ( khz) cr2 cr1 cr0 f osca = 12 mhz f osca = 16 mhz f osca divided by s sla w a data a p 08h 18h 28h mt s sla w a p a p r mr 10h 20h 30h a or a continues 38h 38h a continues 68h other master other master 78h b0h to corresponding states in slave mode successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data arbitration lost in slave address or data byte arbitration lost and addressed as slave byte a or a continues other master data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sscs) corresponds to a defined state of the 2-wire bus
91 7683c?usb?11/07 at83c5134/35/36 table 20-5. status in master transmitter mode status code sssta status of the two- wire bus and two- wire hardware application software response next action taken by two-wire hardware to/from ssdat to sscon sssta sssto ssi ssaa 08h a start condition has been transmitted write sla+w x 0 0 x sla+w will be transmitted. 10h a repeated start condition has been transmitted write sla+w write sla+r xx 00 00 xx sla+w will be transmitted. sla+r will be transmitted. logic will switch to master receiver mode 18h sla+w has been transmitted; ack has been received write data byte no ssdat action no ssdat action no ssdat action 01 0 1 00 1 1 00 0 0 xx x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 20h sla+w has been transmitted; not ack has been received write data byte no ssdat action no ssdat action no ssdat action 01 0 1 00 1 1 00 0 0 xx x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 28h data byte has been transmitted; ack has been received write data byte no ssdat action no ssdat action no ssdat action 01 0 1 00 1 1 00 0 0 xx x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 30h data byte has been transmitted; not ack has been received write data byte no ssdat action no ssdat action no ssdat action 01 0 1 00 1 1 00 0 0 xx x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 38h arbitration lost in sla+w or data bytes no ssdat action no ssdat action 01 00 00 xx two-wire bus will be released and not addressed slave mode will be entered. a start condition will be transmitted when the bus becomes free.
92 7683c?usb?11/07 at83c5134/35/36 figure 20-5. format and state in the master receiver mode s sla r a data 08h 40h 58h s sla r a p w mt 10h 48h a or a continues 38h 38h a continues 68h other master other master 78h b0h to corresponding states in slave mode successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost and addressed as slave a continues other master n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sscs) corresponds to a defined state of the 2-wire bus a data p a 50h mr arbitration lost in slave address or acknowledge bit data a
93 7683c?usb?11/07 at83c5134/35/36 table 20-6. status in master receiver mode status code sssta status of the two- wire bus and two- wire hardware application software response next action taken by two-wire hardware to/from ssdat to sscon sssta sssto ssi ssaa 08h a start condition has been transmitted write sla+r x 0 0 x sla+r will be transmitted. 10h a repeated start condition has been transmitted write sla+r write sla+w xx 00 00 xx sla+r will be transmitted. sla+w will be transmitted. logic will switch to master transmitter mode. 38h arbitration lost in sla+r or not ack bit no ssdat action no ssdat action 01 00 00 xx two-wire bus will be released and not addressed slave mode will be entered. a start condition will be transmitted when the bus becomes free. 40h sla+r has been transmitted; ack has been received no ssdat action no ssdat action 00 00 00 01 data byte will be received and not ack will be returned. data byte will be received and ack will be returned . 48h sla+r has been transmitted; not ack has been received no ssdat action no ssdat action no ssdat action 10 1 01 1 00 0 xx x repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 50h data byte has been received; ack has been returned read data byte read data byte 00 00 00 01 data byte will be received and not ack will be returned. data byte will be received and ack will be returned . 58h data byte has been received; not ack has been returned read data byte read data byte read data byte 10 1 01 1 00 0 xx x repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset.
94 7683c?usb?11/07 at83c5134/35/36 figure 20-6. format and state in the slave receiver mode s sla w a data a data p or s a p or s a general call a data a data p or s a a 60h 68h 80h 80h a0h 88h 70h 90h 90h a0h p or s a 98h a 78h data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sscs) corresponds to a defined state of the 2-wire bus reception of the own slave address and one or more data bytes. all are acknowledged. last data byte received is not acknowledged. arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes. last data byte received is not acknowledged. arbitration lost as master and addressed as slave by general call
95 7683c?usb?11/07 at83c5134/35/36 table 20-7. status in slave receiver mode status code (sscs) status of the 2-wire bus and 2-wire hardware application software response next action taken by 2-wire software to/from ssdat to sscon sta sto si aa 60h own sla+w has been received; ack has been returned no ssdat action or no ssdat action xx 00 00 01 data byte will be received and not ack will be returned data byte will be received and ack will be returned 68h arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no ssdat action or no ssdat action xx 00 00 01 data byte will be received and not ack will be returned data byte will be received and ack will be returned 70h general call address has been received; ack has been returned no ssdat action or no ssdat action xx 00 00 01 data byte will be received and not ack will be returned data byte will be received and ack will be returned 78h arbitration lost in sla+r/w as master; general call address has been received; ack has been returned no ssdat action or no ssdat action xx 00 00 01 data byte will be received and not ack will be returned data byte will be received and ack will be returned 80h previously addressed with own sla+w; data has been received; ack has been returned no ssdat action or no ssdat action xx 00 00 01 data byte will be received and not ack will be returned data byte will be received and ack will be returned 88h previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 00 1 1 00 0 0 00 0 0 01 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1 switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1. a start condition will be transmitted when the bus becomes free 90h previously addressed with general call; data has been received; ack has been returned read data byte or read data byte xx 00 00 01 data byte will be received and not ack will be returned data byte will be received and ack will be returned
96 7683c?usb?11/07 at83c5134/35/36 98h previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 00 1 1 00 0 0 00 0 0 01 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1 switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1. a start condition will be transmitted when the bus becomes free a0h a stop condition or repeated start condition has been received while still addressed as slave no ssdat action or no ssdat action or no ssdat action or no ssdat action 00 1 1 00 0 0 00 0 0 01 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1 switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1. a start condition will be transmitted when the bus becomes free table 20-7. status in slave receiver mode (continued) status code (sscs) status of the 2-wire bus and 2-wire hardware application software response next action taken by 2-wire software to/from ssdat to sscon sta sto si aa
97 7683c?usb?11/07 at83c5134/35/36 figure 20-7. format and state in the slave transmitter mode s sla r a data a data p or s a a8h b8h c0h p or s a c8h all 1?s a b0h data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sscs) corresponds to a defined state of the 2-wire bus reception of the own slave address and one or more data bytes arbitration lost as master and addressed as slave last data byte transmitted. switched to not addressed slave (aa=0) table 20-8. status in slave transmitter mode status code (sscs) status of the 2-wire bus and 2-wire hardware application software response next action taken by 2-wire software to/from ssdat to sscon sta sto si aa a8h own sla+r has been received; ack has been returned load data byte or load data byte xx 00 00 01 last data byte will be transmitted and not ack will be received data byte will be transmitted and ack will be received b0h arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned load data byte or load data byte xx 00 00 01 last data byte will be transmitted and not ack will be received data byte will be transmitted and ack will be received b8h data byte in ssdat has been transmitted; not ack has been received load data byte or load data byte xx 00 00 01 last data byte will be transmitted and not ack will be received data byte will be transmitted and ack will be received
98 7683c?usb?11/07 at83c5134/35/36 table 20-9. miscellaneous status c0h data byte in ssdat has been transmitted; not ack has been received no ssdat action or no ssdat action or no ssdat action or no ssdat action 00 1 1 00 0 0 00 0 0 01 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1 switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1. a start condition will be transmitted when the bus becomes free c8h last data byte in ssdat has been transmitted (aa=0); ack has been received no ssdat action or no ssdat action or no ssdat action or no ssdat action 00 1 1 00 0 0 00 0 0 01 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1 switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognised; gca will be recognised if gc=logic 1. a start condition will be transmitted when the bus becomes free table 20-8. status in slave transmitter mode (continued) status code (sscs) status of the 2-wire bus and 2-wire hardware application software response next action taken by 2-wire software to/from ssdat to sscon sta sto si aa status code (sscs) status of the 2-wire bus and 2-wire hardware application software response next action taken by 2-wire software to/from ssdat to sscon sta sto si aa f8h no relevant state information available; si= 0 no ssdat action no sscon action wait or proceed curre nt transfer 00h bus error due to an illegal start or stop condition no ssdat action 0 1 0 x only the internal hardware is affected, no stop condition is sent on the bus. in all cases, the bus is released and sto is reset.
99 7683c?usb?11/07 at83c5134/35/36 20.3 registers table 20-10. sscon register sscon - synchronous serial control register (93h) 7 6 5 4 3 2 1 0 cr2 ssie sta sto si aa cr1 cr0 bit number bit mnemonic description 7 cr2 control rate bit 2 see . 6 ssie synchronous serial interface enable bit clear to disable sslc. set to enable sslc. 5 sta start flag set to send a start condition on the bus. 4 st0 stop flag set to send a stop condition on the bus. 3 si synchronous serial interrupt flag set by hardware when a serial interrupt is requeste d. must be cleared by software to acknowledge interrup t. 2 aa assert acknowledge flag clear in master and slave receiver modes, to force a not acknowledge (high level on sda). clear to disable sla or gca recognition. set to recognise sla or gca (if gc set) for enterin g slave receiver or transmitter modes. set in master and slave receiver modes, to force an acknowledge (low level on sda). this bit has no effect when in master transmitter m ode. 1 cr1 control rate bit 1 see table 20-4 0 cr0 control rate bit 0 see table 20-4 table 20-11. ssdat (095h) - synchronous serial data register (re ad/write) sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 7 6 5 4 3 2 1 0 bit number bit mnemonic description 7 sd7 address bit 7 or data bit 7. 6 sd6 address bit 6 or data bit 6. 5 sd5 address bit 5 or data bit 5. 4 sd4 address bit 4 or data bit 4. 3 sd3 address bit 3 or data bit 3. 2 sd2 address bit 2 or data bit 2.
100 7683c?usb?11/07 at83c5134/35/36 1 sd1 address bit 1 or data bit 1. 0 sd0 address bit 0 (r/w) or data bit 0. table 20-12. sscs (094h) read - synchronous serial control and s tatus register 7 6 5 4 3 2 1 0 sc4 sc3 sc2 sc1 sc0 0 0 0 bit number bit mnemonic description 0 0 always zero 1 0 always zero 2 0 always zero 3 sc0 status code bit 0 see table 20-5 to table 20-9 4 sc1 status code bit 1 see table 20-5 to table 20-9 5 sc2 status code bit 2 see table 20-5 to table 20-9 6 sc3 status code bit 3 see table 20-5 to table 20-9 7 sc4 status code bit 4 see table 20-5 to table 20-9 table 20-13. ssadr (096h) - synchronous serial address register (read/write) 7 6 5 4 3 2 1 0 a7 a6 a5 a4 a3 a2 a1 a0 bit number bit mnemonic description 7 a7 slave address bit 7. 6 a6 slave address bit 6. 5 a5 slave address bit 5. 4 a4 slave address bit 4. 3 a3 slave address bit 3. 2 a2 slave address bit 2. 1 a1 slave address bit 1. 0 gc general call bit clear to disable the general call address recogniti on. set to enable the general call address recognition. bit number bit mnemonic description
101 7683c?usb?11/07 at83c5134/35/36 21. usb controller . 21.1 description the usb device controller provides the hardware tha t the at89c5131 needs to interface a usb link to a data flow stored in a double port memory (dpram). the usb controller requires a 48 mhz 0.25% referen ce clock, which is the output of the at89c5131 pll (see section ?pll?, page 14) divided by a clock prescaler. this clock is used to generate a 12 mhz full-speed bit clock from the rec eived usb differential data and to transmit data according to full speed usb device tolerance. clock recovery is done by a digital phase locked loop (dpll) block, which is compliant with t he jitter specification of the usb bus. the serial interface engine (sie) block performs nr zi encoding and decoding, bit stuffing, crc generation and checking, and the serial-parallel da ta conversion. the universal function interface (ufi) realizes the interface between the data flow and the dual port ram. figure 21-1. usb device controller block diagram 21.1.1 serial interface engine (sie) the sie performs the following functions: ? nrzi data encoding and decoding. ? bit stuffing and un-stuffing. ? crc generation and checking. ? handshakes. ? token type identifying. sie dpll usb d+/d- buffer ufi 12 mhz 48 mhz +/- 0.25% d+ up to 48 mhz uc_sysclk c51 microcontroller interface d-
102 7683c?usb?11/07 at83c5134/35/36 ? address checking. ? clock generation (via dpll). figure 21-2. sie block diagram 21.1.2 function interface unit (fiu) the function interface unit provides the interface between the at89c5131 and the sie. it man- ages transactions at the packet level with minimal intervention from the device firmware, which reads and writes the endpoint fifos. end of packet detection start of packet detection d+ d- clock recovery sync detection pid decoder address decoder serial to p a r a l l e l crc5 and crc16 generation/check usb pattern generator parallel to serial converter bit stuffing nrzi converter crc16 generator nrzi ?nrz bit un-stuffing packet bit counter clk48 (48 mhz) sysclk (12 mhz) datain [7:0] dataout 8 8
103 7683c?usb?11/07 at83c5134/35/36 figure 21-3. ufi block diagram figure 21-4. minimum intervention from the usb device firmware 21.2 configuration 21.2.1 general configuration ? usb controller enable before any usb transaction, the 48 mhz required by the usb controller must be correctly generated ( see ?clock controller? on page 13. ). the usb controller will be then enabled by setting the eusb bit in the usbcon register. ? set address after a reset or a usb reset, the software has to s et the fen (function enable) bit in the usbaddr register. this action will allow the usb co ntroller to answer to the requests sent at the address 0. when a set_address request has been received, the u sb controller must only answer to the address defined by the request. the new addr ess will be stored in the usbaddr reg- ister. the fen bit and the fadden bit in the usbcon register will be set to allow the usb controller to answer only to requests sent at the n ew address. transfer control fsm dpr control usb side csreg 0 to 7 registers bank dpr control mp side fiu user dpram up to 48 mhz uc_sysclk c51 microcontroller interface asynchronous information transfer endpoint 0 endpoint 1 endpoint 2 endpoint 3 sie dpll endpoint 4 endpoint 5 out transactions: host ufi c51 out data0 (n bytes) ack endpoint fifo read (n bytes) out data1 nack out data1 ack in transactions: host ufi c51 in ack endpoint fifo write in data1 nack interrupt c51 in data1 interrupt c51 endpoint fifo write
104 7683c?usb?11/07 at83c5134/35/36 ? set configuration the confg bit in the usbcon register has to be set after a set_configuration request with a non-zero value. otherwise, this bit has to be cleared. 21.2.2 endpoint configuration ? selection of an endpoint the endpoint register access is performed using the uepnum register. the registers ? uepstax ? uepconx ? uepdatx ? ubyctlx ? ubycthx these registers correspond to the endpoint whose nu mber is stored in the uepnum regis- ter. to select an endpoint, the firmware has to wri te the endpoint number in the uepnum register. figure 21-5. endpoint selection ? endpoint enable before using an endpoint, this one will be enabled by setting the epen bit in the uepconx register. an endpoint which is not enabled won?t answer to an y usb request. the default control endpoint (endpoint 0) will always be enabled in ord er to answer to usb standard requests. ? endpoint type configuration all standard endpoints can be configured in control , bulk, interrupt or isochronous mode. the ping-pong endpoints can be configured in bulk, interrupt or isochronous mode. the configuration of an endpoint is performed by settin g the field eptype with the following values: ? control:eptype = 00b ? isochronous:eptype = 01b ? bulk:eptype = 10b ? interrupt:eptype = 11b uepnum endpoint 0 endpoint 5 uepsta0 uepcon0 uepdat0 uepsta5 uepcon5 uepdat5 01 2 3 4 5 sfr registers uepstax uepconx uepdatx x ubycth0 ubyctl0 ubycth5 ubyctl5 ubycthx ubyctlx
105 7683c?usb?11/07 at83c5134/35/36 the endpoint 0 is the default control endpoint and will always be configured in control type. ? endpoint direction configuration for bulk, interrupt and isochronous endpoints, the direction is defined with the epdir bit of the uepconx register with the following values: ? in:epdir = 1b ? out:epdir = 0b for control endpoints, the epdir bit has no effect. ? summary of endpoint configuration: do not forget to select the correct endpoint number in the uepnum register before access- ing to endpoint specific registers. table 21-1. summary of endpoint configuration ? endpoint fifo reset before using an endpoint, its fifo will be reset. t his action resets the fifo pointer to its original value, resets the byte counter of the endp oint (ubyctlx and ubycthx registers), and resets the data toggle bit (dtgl bit in uepconx ). the reset of an endpoint fifo is performed by setti ng to 1 and resetting to 0 the corre- sponding bit in the ueprst register. for example, in order to reset the endpoint number 2 fifo, write 0000 0100b then 0000 0000b in the ueprst register. note that the endpoint reset doesn?t reset the bank number for ping-pong endpoints. 21.3 read/write data fifo 21.3.1 fifo mapping depending on the selected endpoint through the uepn um register, the uepdatx register allows to access the corresponding endpoint data fi fo. endpoint configuration epen epdir eptype uepconx disabled 0b xb xxb 0xxx xxxb control 1b xb 00b 80h bulk-in 1b 1b 10b 86h bulk-out 1b 0b 10b 82h interrupt-in 1b 1b 11b 87h interrupt-out 1b 0b 11b 83h isochronous-in 1b 1b 01b 85h isochronous-out 1b 0b 01b 81h
106 7683c?usb?11/07 at83c5134/35/36 figure 21-6. endpoint fifo configuration 21.3.2 read data fifo the read access for each out endpoint is performed using the uepdatx register. after a new valid packet has been received on an en dpoint, the data are stored into the fifo and the byte counter of the endpoint is updated (ub yctlx and ubycthx registers). the firm- ware has to store the endpoint byte counter before any access to the endpoint fifo. the byte counter is not updated when reading the fifo. to read data from an endpoint, select the correct e ndpoint number in uepnum and read the uepdatx register. this action automatically decreas es the corresponding address vector, and the next data is then available in the uepdatx regi ster. 21.3.3 write data fifo the write access for each in endpoint is performed using the uepdatx register. to write a byte into an in endpoint fifo, select th e correct endpoint number in uepnum and write into the uepdatx register. the corresponding address vector is automatically increased, and another write can be carried out. warning 1: the byte counter is not updated. warning 2: do not write more bytes than supported b y the corresponding endpoint. 21.4 bulk/interrupt transactions bulk and interrupt transactions are managed in the same way. uepnum endpoint 0 endpoint 5 uepsta0 uepcon0 uepdat0 uepsta5 uepcon5 uepdat5 01 2 3 4 5 sfr registers uepstax uepconx uepdatx x ubycth0 ubyctl0 ubycth5 ubyctl5 ubycthx ubyctlx
107 7683c?usb?11/07 at83c5134/35/36 21.4.1 bulk/interrupt out transactions in standard m ode figure 21-7. bulk/interrupt out transactions in standard mode an endpoint will be first enabled and configured be fore being able to receive bulk or interrupt packets. when a valid out packet is received on an endpoint, the rxoutb0 bit is set by the usb con- troller. this triggers an interrupt if enabled. the firmware has to select the corresponding endpoint, store the number of data bytes by reading the ubyctlx and ubycthx registers. if the received packet is a zlp (zero length packet), the ubyctlx and ubycthx register val- ues are equal to 0 and no data has to be read. when all the endpoint fifo bytes have been read, th e firmware will clear the rxoutb0 bit to allow the usb controller to accept the next out pac ket on this endpoint. until the rxoutb0 bit has been cleared by the firmware, the usb controlle r will answer a nak handshake for each out requests. if the host sends more bytes than supported by the endpoint fifo, the overflow data won?t be stored, but the usb controller will consider that t he packet is valid if the crc is correct and the endpoint byte counter contains the number of bytes sent by the host. out data0 (n bytes) ack host ufi c51 endpoint fifo read byte 1 out data1 nak rxoutb0 endpoint fifo read byte 2 endpoint fifo read byte n clear rxoutb0 out data1 nak out data1 ack rxoutb0 endpoint fifo read byte 1
108 7683c?usb?11/07 at83c5134/35/36 21.4.2 bulk/interrupt out transactions in ping-pong mode figure 21-8. bulk/interrupt out transactions in ping-pong mode an endpoint will be first enabled and configured be fore being able to receive bulk or interrupt packets. when a valid out packet is received on the endpoint bank 0, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabl ed. the firmware has to select the correspond- ing endpoint, store the number of data bytes by rea ding the ubyctlx and ubycthx registers. if the received packet is a zlp (zero length packet ), the ubyctlx and ubycthx register val- ues are equal to 0 and no data has to be read. when all the endpoint fifo bytes have been read, th e firmware will clear the rxoub0 bit to allow the usb controller to accept the next out pac ket on the endpoint bank 0. this action switches the endpoint bank 0 and 1. until the rxout b0 bit has been cleared by the firmware, the usb controller will answer a nak handshake for each out requests on the bank 0 endpoint fifo. when a new valid out packet is received on the endp oint bank 1, the rxoutb1 bit is set by the usb controller. this triggers an interrupt if e nabled. the firmware empties the bank 1 end- point fifo before clearing the rxoutb1 bit. until t he rxoutb1 bit has been cleared by the firmware, the usb controller will answer a nak hand shake for each out requests on the bank 1 endpoint fifo. the rxoutb0 and rxoutb1 bits are alternatively set by the usb controller at each new valid packet receipt. the firmware has to clear one of these two bits aft er having read all the data fifo to allow a new valid packet to be stored in the corresponding bank . out data0 (n bytes) ack host ufi c51 endpoint fifo bank 0 - read byte 1 rxoutb0 endpoint fifo bank 0 - read byte 2 endpoint fifo bank 0 - read byte n clear rxoutb0 out data1 (m bytes) ack rxoutb1 endpoint fifo bank 1 - read byte 1 endpoint fifo bank 1 - read byte 2 endpoint fifo bank 1 - read byte m clear rxoutb1 out data0 (p bytes) ack rxoutb0 endpoint fifo bank 0 - read byte 1 endpoint fifo bank 0 - read byte 2 endpoint fifo bank 0 - read byte p clear rxoutb0
109 7683c?usb?11/07 at83c5134/35/36 a nak handshake is sent by the usb controller only if the banks 0 and 1 has not been released by the firmware. if the host sends more bytes than supported by the endpoint fifo, the overflow data won?t be stored, but the usb controller will consider that t he packet is valid if the crc is correct. 21.4.3 bulk/interrupt in transactions in standard mo de figure 21-9. bulk/interrupt in transactions in standard mode an endpoint will be first enabled and configured be fore being able to send bulk or interrupt packets. the firmware will fill the fifo with the data to be sent and set the txrdy bit in the uepstax register to allow the usb controller to send the da ta stored in fifo at the next in request con- cerning this endpoint. to send a zero length packet , the firmware will set the txrdy bit without writing any data into the endpoint fifo. until the txrdy bit has been set by the firmware, t he usb controller will answer a nak hand- shake for each in requests. to cancel the sending of this packet, the firmware has to reset the txrdy bit. the packet stored in the endpoint fifo is then cleared and a new pack et can be written and sent. when the in packet has been sent and acknowledged b y the host, the txcmpl bit in the uep- stax register is set by the usb controller. this tr iggers a usb interrupt if enabled. the firmware will clear the txcmpl bit before filling the endpoi nt fifo with new data. the firmware will never write more bytes than suppo rted by the endpoint fifo. all usb retry mechanisms are automatically managed by the usb controller. in data0 (n bytes) ack host ufi c51 endpoint fifo write byte 1 in nak txcmpl endpoint fifo write byte 2 endpoint fifo write byte n set txrdy clear txcmpl endpoint fifo write byte 1
110 7683c?usb?11/07 at83c5134/35/36 21.4.4 bulk/interrupt in transactions in ping-pong m ode figure 21-10. bulk/interrupt in transactions in ping-pong mode an endpoint will be first enabled and configured be fore being able to send bulk or interrupt packets. the firmware will fill the fifo bank 0 with the dat a to be sent and set the txrdy bit in the uep- stax register to allow the usb controller to send t he data stored in fifo at the next in request concerning the endpoint. the fifo banks are automat ically switched, and the firmware can immediately write into the endpoint fifo bank 1. when the in packet concerning the bank 0 has been s ent and acknowledged by the host, the txcmpl bit is set by the usb controller. this trigg ers a usb interrupt if enabled. the firmware will clear the txcmpl bit before filling the endpoi nt fifo bank 0 with new data. the fifo banks are then automatically switched. when the in packet concerning the bank 1 has been s ent and acknowledged by the host, the txcmpl bit is set by the usb controller. this trigg ers a usb interrupt if enabled. the firmware will clear the txcmpl bit before filling the endpoi nt fifo bank 1 with new data. the bank switch is performed by the usb controller each time the txrdy bit is set by the firm- ware. until the txrdy bit has been set by the firmw are for an endpoint bank, the usb controller will answer a nak handshake for each in requests co ncerning this bank. note that in the example above, the firmware clears the transmit complete bit (txcmpl) before setting the transmit ready bit (txrdy). this is don e in order to avoid the firmware to clear at the same time the txcmpl bit for bank 0 and the ban k 1. in data0 (n bytes) ack host ufi c51 endpoint fifo bank 0 - write byte 1 in nack txcmpl endpoint fifo bank 0 - write byte 2 endpoint fifo bank 0 - write byte n set txrdy endpoint fifo bank 1 - write byte 1 endpoint fifo bank 1 - write byte 2 endpoint fifo bank 1 - write byte m set txrdy in data1 (m bytes) ack endpoint fifo bank 0 - write byte 1 endpoint fifo bank 0 - write byte 2 endpoint fifo bank 0 - write byte p set txrdy clear txcmpl in data0 (p bytes) ack txcmpl clear txcmpl endpoint fifo bank 1 - write byte 1
111 7683c?usb?11/07 at83c5134/35/36 the firmware will never write more bytes than suppo rted by the endpoint fifo. 21.5 control transactions 21.5.1 setup stage the dir bit in the uepstax register will be at 0. receiving setup packets is the same as receiving bu lk out packets, except that the rxsetup bit in the uepstax register is set by the usb contr oller instead of the rxoutb0 bit to indicate that an out packet with a setup pid has been receiv ed on the control endpoint. when the rxsetup bit has been set, all the other bits of the uepstax register are cleared and an inter- rupt is triggered if enabled. the firmware has to read the setup request stored i n the control endpoint fifo before clearing the rxsetup bit to free the endpoint fifo for the n ext transaction. 21.5.2 data stage: control endpoint direction the data stage management is similar to bulk manage ment. a control endpoint is managed by the usb controller as a full-duplex endpoint: in and out. all other endpoint types are managed as half-duplex end point: in or out. the firmware has to specify the control endpoint direction for the data stage using the dir bit in the uepstax regis- ter. the firmware has to use the dir bit before data in in order to meet the data-toggle requirements: ? if the data stage consists of ins, the firmware has to set the dir bit in the uepstax register before writing into the fifo and sending the data by setting to 1 the txrdy bit in t he uepstax register. the in transaction is complete when the txcmpl has been set by the har dware. the firmware will clear the txcmpl bit before any other transaction. ? if the data stage consists of outs, the firmware has to leave the dir bit at 0. the rxo utb0 bit is set by hardware when a new valid packet has been received on the endpoint. the firmware must read the data stored into the fifo and then clear the rxoutb0 bit to reset th e fifo and to allow the next transaction. to send a stall handshake, see ?stall handshake? on page 114 . 21.5.3 status stage the dir bit in the uepstax register will be reset a t 0 for in and out status stage. the status stage management is similar to bulk mana gement. ? for a control write transaction or a no-data contr ol transaction, the status stage consists of a in zero length packet (see ?bulk/interrupt in transactions in standard mode? o n page 109 ). to send a stall handshake, see ?stall handshake? on page 114 . ? for a control read transaction, the status stage c onsists of a out zero length packet (see ?bulk/interrupt out transactions in standard mode? on page 107 ).
112 7683c?usb?11/07 at83c5134/35/36 21.6 isochronous transactions 21.6.1 isochronous out transactions in standard mode an endpoint will be first enabled and configured be fore being able to receive isochronous packets. when a out packet is received on an endpoint, the r xoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the corresponding endpoint, store the number of data bytes by reading the ubyct lx and ubycthx registers. if the received packet is a zlp (zero length packet), the ubyctlx and ubycthx register values are equal to 0 and no data has to be read. the stlcrc bit in the uepstax register is set by th e usb controller if the packet stored in fifo has a corrupted crc. this bit is updated after each new packet receipt. when all the endpoint fifo bytes have been read, th e firmware will clear the rxoutb0 bit to allow the usb controller to store the next out pack et data into the endpoint fifo. until the rxoutb0 bit has been cleared by the firmware, the d ata sent by the host at each out transac- tion will be lost. if the rxoutb0 bit is cleared while the host is sen ding data, the usb controller will store only the remaining bytes into the fifo. if the host sends more bytes than supported by the endpoint fifo, the overflow data won?t be stored, but the usb controller will consider that t he packet is valid if the crc is correct. 21.6.2 isochronous out transactions in ping-pong mod e an endpoint will be first enabled and configured be fore being able to receive isochronous packets. when a out packet is received on the endpoint bank 0, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the corresponding endpoint, store the number of data bytes by reading the ubyctlx and ubycthx registers. if the received packet is a zlp (zero length packet), the ubyctlx and ubycthx register val- ues are equal to 0 and no data has to be read. the stlcrc bit in the uepstax register is set by th e usb controller if the packet stored in fifo has a corrupted crc. this bit is updated after each new packet receipt. when all the endpoint fifo bytes have been read, th e firmware will clear the rxoub0 bit to allow the usb controller to store the next out pack et data into the endpoint fifo bank 0. this action switches the endpoint bank 0 and 1. until th e rxoutb0 bit has been cleared by the firm- ware, the data sent by the host on the bank 0 endpo int fifo will be lost. if the rxoutb0 bit is cleared while the host is sen ding data on the endpoint bank 0, the usb controller will store only the remaining bytes into the fifo. when a new out packet is received on the endpoint b ank 1, the rxoutb1 bit is set by the usb controller. this triggers an interrupt if enabl ed. the firmware empties the bank 1 endpoint fifo before clearing the rxoutb1 bit. until the rxo utb1 bit has been cleared by the firm- ware, the data sent by the host on the bank 1 endpo int fifo will be lost. the rxoutb0 and rxoutb1 bits are alternatively set by the usb controller at each new packet receipt.
113 7683c?usb?11/07 at83c5134/35/36 the firmware has to clear one of these two bits aft er having read all the data fifo to allow a new packet to be stored in the corresponding bank. if the host sends more bytes than supported by the endpoint fifo, the overflow data won?t be stored, but the usb controller will consider that t he packet is valid if the crc is correct. 21.6.3 isochronous in transactions in standard mode an endpoint will be first enabled and configured be fore being able to send isochronous packets. the firmware will fill the fifo with the data to be sent and set the txrdy bit in the uepstax register to allow the usb controller to send the da ta stored in fifo at the next in request con- cerning this endpoint. if the txrdy bit is not set when the in request occ urs, nothing will be sent by the usb controller. when the in packet has been sent, the txcmpl bit in the uepstax register is set by the usb controller. this triggers a usb interrupt if enable d. the firmware will clear the txcmpl bit before filling the endpoint fifo with new data. the firmware will never write more bytes than suppo rted by the endpoint fifo 21.6.4 isochronous in transactions in ping-pong mode an endpoint will be first enabled and configured be fore being able to send isochronous packets. the firmware will fill the fifo bank 0 with the dat a to be sent and set the txrdy bit in the uep- stax register to allow the usb controller to send t he data stored in fifo at the next in request concerning the endpoint. the fifo banks are automat ically switched, and the firmware can immediately write into the endpoint fifo bank 1. if the txrdy bit is not set when the in request occ urs, nothing will be sent by the usb controller. when the in packet concerning the bank 0 has been s ent, the txcmpl bit is set by the usb controller. this triggers a usb interrupt if enable d. the firmware will clear the txcmpl bit before filling the endpoint fifo bank 0 with new da ta. the fifo banks are then automatically switched. when the in packet concerning the bank 1 has been s ent, the txcmpl bit is set by the usb controller. this triggers a usb interrupt if enable d. the firmware will clear the txcmpl bit before filling the endpoint fifo bank 1 with new da ta. the bank switch is performed by the usb controller each time the txrdy bit is set by the firm- ware. until the txrdy bit has been set by the firmw are for an endpoint bank, the usb controller won?t send anything at each in requests concerning this bank. the firmware will never write more bytes than suppo rted by the endpoint fifo. 21.7 miscellaneous 21.7.1 usb reset the eorint bit in the usbint register is set by har dware when a end of reset has been detected on the usb bus. this triggers a usb interr upt if enabled. the usb controller is still enabled, but all the usb registers are reset by har dware. the firmware will clear the eorint bit to allow the next usb reset detection.
114 7683c?usb?11/07 at83c5134/35/36 21.7.2 stall handshake this function is only available for control, bulk, and interrupt endpoints. the firmware has to set the stallrq bit in the ueps tax register to send a stall handshake at the next request of the host on the endpoint sel ected with the uepnum register. the rxsetup, txrdy, txcmpl, rxoutb0 and rxoutb1 bits mu st be first reset to 0. the bit stlcrc is set at 1 by the usb controller when a sta ll has been sent. this triggers an inter- rupt if enabled. the firmware will clear the stallrq and stlcrc bits after each stall sent. the stallrq bit is cleared automatically by hardwar e when a valid setup pid is received on a control type endpoint. important note: when a clear halt feature occurs fo r an endpoint, the firmware will reset this endpoint using the ueprst register in order to rese t the data toggle management. 21.7.3 start of frame detection the sofint bit in the usbint register is set when t he usb controller detects a start of frame pid. this triggers an interrupt if enabled. the fir mware will clear the sofint bit to allow the next start of frame detection. 21.7.4 frame number when receiving a start of frame, the frame number i s automatically stored in the ufnuml and ufnumh registers. the crcok and crcerr bits indicat e if the crc of the last start of frame is valid (crcok set at 1) or corrupted (crcer r set at 1). the ufnuml and ufnumh registers are automatically updated when receiving a new start of frame. 21.7.5 data toggle bit the data toggle bit is set by hardware when a data0 packet is received and accepted by the usb controller and cleared by hardware when a data1 packet is received and accepted by the usb controller. this bit is reset when the firmware resets the endpoint fifo using the ueprst register. for control endpoints, each setup transaction start s with a data0 and data toggling is then used as for bulk endpoints until the end of the dat a stage (for a control write transfer). the sta- tus stage completes the data transfer with a data1 (for a control read transfer). for isochronous endpoints, the device firmware will ignore the data-toggle. 21.8 suspend/resume management 21.8.1 suspend the suspend state can be detected by the usb contro ller if all the clocks are enabled and if the usb controller is enabled. the bit spint is set by hardware when an idle state is detected for more than 3 ms. this triggers a usb interrupt if en abled. in order to reduce current consumption, the firmwar e can put the usb pad in idle mode, stop the clocks and put the c51 in idle or power-down mo de. the resume detection is still active. the usb pad is put in idle mode when the firmware c lear the spint bit. in order to avoid a new suspend detection 3ms later, the firmware has to di sable the usb clock input using the susp- clk bit in the usbcon register. the usb pad automat ically exits of idle mode when a wake- up event is detected.
115 7683c?usb?11/07 at83c5134/35/36 the stop of the 48 mhz clock from the pll should be done in the following order: 1. clear suspend interrupt bit in usbint (required t o allow the usb pads to enter power down mode). 2. enable usb resume interrupt. 3. disable of the 48 mhz clock input of the usb cont roller by setting to 1 the suspclk bit in the usbcon register. 4. disable the pll by clearing the pllen bit in the pllcon register. 5. make the cpu core enter power down mode by settin g pdown bit in pcon. 21.8.2 resume when the usb controller is in suspend state, the re sume detection is active even if all the clocks are disabled and if the c51 is in idle or po wer-down mode. the wupcpu bit is set by hardware when a non-idle state occurs on the usb bu s. this triggers an interrupt if enabled. this interrupt wakes up the cpu from its idle or po wer-down state and the interrupt function is then executed. the firmware will first enable the 4 8 mhz generation and then reset to 0 the suspclk bit in the usbcon register if needed. the firmware has to clear the spint bit in the usbi nt register before any other usb operation in order to wake up the usb controller from its sus pend mode. the usb controller is then re-activated. figure 21-11. example of a suspend/resume management usb controller init detection of a suspend state spint set suspclk disable pll microcontroller in power-down detection of a resume state wupcpu enable pll clear suspclk clear wupcpu bit clear spint
116 7683c?usb?11/07 at83c5134/35/36 21.8.3 upstream resume a usb device can be allowed by the host to send an upstream resume for remote wake up purpose. when the usb controller receives the set_feature re quest: device_remote_wakeup, the firmware will set to 1 the rmwupe bit in the us bcon register to enable this functionality. rmwupe value will be 0 in the other cases. if the device is in suspend mode, the usb controlle r can send an upstream resume by clear- ing first the spint bit in the usbint register and by setting then to 1 the sdrmwup bit in the usbcon register. the usb controller sets to 1 the u prsm bit in the usbcon register. all clocks must be enabled first. the remote wake is se nt only if the usb bus was in suspend state for at least 5 ms. when the upstream resume i s completed, the uprsm bit is reset to 0 by hardware. the firmware will then clear the sdrmwup bit. figure 21-12. example of remote wakeup management usb controller init detection of a suspend state spint set rmwupe suspend management enable clocks upstream resume sent uprsm clear spint set sdmwup clear sdrmwup set_feature: device_remote_wakeup need usb resume uprsm = 1
117 7683c?usb?11/07 at83c5134/35/36 21.9 detach simulation in order to be re-enumerated by the host, the at83c 5134/35/36 has the possibility to simulate a detach - attach of the usb bus. the v ref output voltage is between 3.0v and 3.6v. this outp ut can be connected to the d+ pull- up as shown in figure 21-13 . this output can be put in high-impedance when the detach bit is set to 1 in the usbcon register. maintaining this o utput in high impedance for more than 3 s will simulate the disconnection of the device. when resetting the detach bit, an attach is then simulated. figure 21-13. example of v ref connection figure 21-14. disconnect timing 21.10 usb interrupt system 21.10.1 interrupt system priorities figure 21-15. usb interrupt control system d- d+ d- d+ gnd v cc v ref 1.5 kw usb-b connector 12 3 4 at89c5131 d+ d- v ss v il v ihz (min) device disconnected disconnect detected > = 2,5 m s eusb ie1.6 ea ie0.7 usb controller iph/l interrupt enable lowest priority interrupts priority enable 00 01 10 11 d+ d-
118 7683c?usb?11/07 at83c5134/35/36 table 21-2. priority levels 21.10.2 usb interrupt control system as shown in figure 21-16, many events can produce a usb interrupt: ? txcmpl: transmitted in data (see table 21-9 on page 125 ). this bit is set by hardware when the host accept a in packet. ? rxoutb0: received out data bank 0 (see table 21-9 on page 125 ). this bit is set by hardware when an out packet is accepted by the endp oint and stored in bank 0. ? rxoutb1: received out data bank 1 (only for ping-p ong endpoints) (see table 21-9 on page 125 ). this bit is set by hardware when an out packet i s accepted by the endpoint and stored in bank 1. ? rxsetup: received setup (see table 21-9 on page 125 ). this bit is set by hardware when an setup packet is accepted by the endpoint. ? stlcrc: stalled (only for control, bulk and interr upt endpoints) (see table 21-9 on page 125 ). this bit is set by hardware when a stall handsha ke has been sent as requested by stallrq, and is reset by hardware when a setup pack et is received. ? sofint: start of frame interrupt ( see ?usbien register usbien (s:beh) usb global interrupt enable register? on page 122. ). this bit is set by hardware when a usb start of frame packet has been received. ? wupcpu: wake-up cpu interrupt ( see ?usbien register usbien (s:beh) usb global interrupt enable register? on page 122. ). this bit is set by hardware when a usb resume is detected on the usb bus, after a suspend state. ? spint: suspend interrupt ( see ?usbien register usbien (s:beh) usb global inte rrupt enable register? on page 122. ). this bit is set by hardware when a usb suspend i s detected on the usb bus. iphusb iplusb usb priority level 0 0 0 lowest 0 1 1 1 0 2 1 1 3 highest
119 7683c?usb?11/07 at83c5134/35/36 figure 21-16. usb interrupt control block diagram txcmp uepstax.0 rxoutb0 uepstax.1 rxsetup uepstax.2 stlcrc uepstax.3 epxie uepien.x epxint uepint.x sofint usbint.3 esofint usbien.3 spint usbint.0 espint usbien.0 eusb ie1.6 endpoint x (x = 0..5) eorint usbint.4 wupcpu usbint.5 ewupcpu usbien.5 rxoutb1 uepstax.6 eeorint usbien.4
120 7683c?usb?11/07 at83c5134/35/36 21.11 usb registers table 21-3. usbcon register usbcon (s:bch) usb global control register reset value = 00h 7 6 5 4 3 2 1 0 usbe suspclk sdrmwup detach uprsm rmwupe confg fadden bit number bit mnemonic description 7 usbe usb enable set this bit to enable the usb controller. clear this bit to disable and reset the usb control ler, to disable the usb transceiver an to disable the usb controller clock inputs. 6 suspclk suspend usb clock set this bit to disable the 48 mhz clock input (res ume detection is still active). clear this bit to enable the 48 mhz clock input. 5 sdrmwup send remote wake up set this bit to force an external interrupt on the usb controller for remote wake up purpose. an upstream resume is send only if the bit rmwupe i s set, all usb clocks are enabled and the usb bus was in suspend state for at least 5 ms. see uprsm below. this bit is cleared by software. 4 detach detach command set this bit to simulate a detach on the usb line. the v ref pin is then in a floating state. clear this bit to maintain v ref at high level. 3 uprsm upstream resume (read only) this bit is set by hardware when sdrmwup has been s et and if rmwupe is enabled. this bit is cleared by hardware after the upstream resume has been sent. 2 rmwupe remote wake-up enable set this bit to enabled request an upstream resume signaling to the host. clear this bit otherwise. note: do not set this bit if the host has not set t he device_remote_wakeup feature for the device. 1 confg configured this bit will be set by the device firmware after a set_configuration request with a non-zero value has been correctly processed. it will be cleared by the device firmware when a se t_configuration request with a zero value is received. it is cleared by har dware on hardware reset or when an usb reset is detected on the bus (se0 state for at least 32 full speed bit times: typically 2.7 s). 0 fadden function address enable this bit will be set by the device firmware after a successful status phase of a set_address transaction. it will not be cleared afterwards by the device fir mware. it is cleared by hardware on hardware reset or when an usb reset is received (see above). when this bit is cleared, the default function address is used (0).
121 7683c?usb?11/07 at83c5134/35/36 table 21-4. usbint register usbint (s:bdh) usb global interrupt register reset value = 00h 7 6 5 4 3 2 1 0 - - wupcpu eorint sofint - - spint bit number bit mnemonic description 7-6 - reserved the value read from these bits is always 0. do not set these bits. 5 wupcpu wake up cpu interrupt this bit is set by hardware when the usb controller is in suspend state and is re- activated by a non-idle signal from usb line (not b y an upstream resume). this triggers a usb interrupt when ewupcpu is set in table 21-5 on page 122 . when receiving this interrupt, user has to enable a ll usb clock inputs. this bit will be cleared by software (usb clocks mu st be enabled before). 4 eorint end of reset interrupt this bit is set by hardware when a end of reset has been detected by the usb controller. this triggers a usb interrupt when eeor int is set (see figure 21-5 on page 122). this bit will be cleared by software. 3 sofint start of frame interrupt this bit is set by hardware when an usb start of fr ame pid (sof) has been detected. this triggers a usb interrupt when esofint is set ( see table 21-5 on page 122 ). this bit will be cleared by software. 2 - reserved the value read from this bit is always 0. do not se t this bit. 1 - reserved the value read from this bit is always 0. do not se t this bit. 0 spint suspend interrupt this bit is set by hardware when a usb suspend (idl e bus for three frame periods: a j state for 3 ms) is detected. this triggers a usb in terrupt when espint is set in see table 21-5 on page 122 . this bit will be cleared by software before any oth er usb operation to re-activate the macro.
122 7683c?usb?11/07 at83c5134/35/36 table 21-5. usbien register usbien (s:beh) usb global interrupt enable register reset value = 10h 7 6 5 4 3 2 1 0 - - ewupcpu eeorint esofint - - espint bit number bit mnemonic description 7-6 - reserved the value read from these bits is always 0. do not set these bits. 5 ewupcpu enable wake up cpu interrupt set this bit to enable wake up cpu interrupt. ( see ?usbien register usbien (s:beh) usb global interrupt enable register? on pa ge 122. ) clear this bit to disable wake up cpu interrupt. 4 eeofint enable end of reset interrupt set this bit to enable end of reset interrupt. ( see ?usbien register usbien (s:beh) usb global interrupt enable register? on pa ge 122. ). this bit is set after reset. clear this bit to disable end of reset interrupt. 3 esofint enable sof interrupt set this bit to enable sof interrupt. ( see ?usbien register usbien (s:beh) usb global interrupt enable register? on page 122. ). clear this bit to disable sof interrupt. 2 - reserved the value read from these bits is always 0. do not set these bits. 1 - 0 espint enable suspend interrupt set this bit to enable suspend interrupts (see the ?usbien register usbien (s:beh) usb global interrupt enable register? on pa ge 122 ). clear this bit to disable suspend interrupts.
123 7683c?usb?11/07 at83c5134/35/36 table 21-6. usbaddr register usbaddr (s:c6h) usb address register reset value = 80h table 21-7. uepnum register uepnum (s:c7h) usb endpoint number reset value = 00h 7 6 5 4 3 2 1 0 fen uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 bit number bit mnemonic description 7 fen function enable set this bit to enable the address filtering functi on. cleared this bit to disable the function. 6-0 uadd[6:0] usb address this field contains the default address (0) after p ower-up or usb bus reset. it will be written with the value set by a set_addr ess request received by the device firmware. 7 6 5 4 3 2 1 0 - - - - epnum3 epnum2 epnum1 epnum0 bit number bit mnemonic description 7-4 - reserved the value read from these bits is always 0. do not set these bits. 3-0 epnum[3:0] endpoint number set this field with the number of the endpoint whic h will be accessed when reading or writing to, uepdatx register uepdatx (s:cfh) usb fifo data endpoint x (x = epnum set in uepnum register uepnum (s:c7h) usb e ndpoint number), ubyctlx register ubyctlx (s:e2h) usb byte count low register x (x = epnum set in uepnum register uepnum (s:c7h) usb end point number), ubycthx register ubycthx (s:e3h) usb byte count hig h register x (x = epnum set in uepnum register uepnum (s:c7h) usb end point number) or uepconx register uepconx (s:d4h) usb endpoint x con trol register. this value can be 0, 1, 2, 3, 4, or 5.
124 7683c?usb?11/07 at83c5134/35/36 table 21-8. uepconx register uepconx (s:d4h) usb endpoint x control register note: 1. (x = epnum set in uepnum register uepnum (s: c7h) usb endpoint number) reset value = 80h when uepnum = 0 (default control endpoint) reset value = 00h otherwise for all other endpoints 7 6 5 4 3 2 1 0 epen - - - dtgl epdir eptype1 eptype0 bit number bit mnemonic description 7 epen endpoint enable set this bit to enable the endpoint according to th e device configuration. endpoint 0 will always be enabled after a hardware or usb bus reset and participate in the device configuration. clear this bit to disable the endpoint according to the device configuration. 6 - reserved the value read from this bit is always 0. do not se t this bit. 5 - reserved the value read from this bit is always 0. do not se t this bit. 4 - reserved the value read from this bit is always 0. do not se t this bit. 3 dtgl data toggle (read-only) this bit is set by hardware when a valid data0 pack et is received and accepted. this bit is cleared by hardware when a valid data1 packet is received and accepted. 2 epdir endpoint direction set this bit to configure in direction for bulk, in terrupt and isochronous endpoints. clear this bit to configure out direction for bulk, interrupt and isochronous endpoints. this bit has no effect for control endpoints. 1-0 eptype[1:0] endpoint type set this field according to the endpoint configurat ion (endpoint 0 will always be configured as control): 00control endpoint 01isochronous endpoint 10bulk endpoint 11interrupt endpoint
125 7683c?usb?11/07 at83c5134/35/36 reset value = 00h table 21-9. uepstax (s:ceh) usb endpoint x status register 7 6 5 4 3 2 1 0 dir rxoutb1 stallrq txrdy stl/crc rxsetup rxoutb0 txcmp bit number bit mnemonic description 7 dir control endpoint direction this bit is used only if the endpoint is configured in the control type (seesection ?uepconx register u epconx (s:d4h) usb endpoint x control register?). this bit determines the control data and status dir ection. the device firmware will set this bit only for the in data stage, before any other usb operation. othe rwise, the device firmware will clear this bit. 6 rxoutb1 received out data bank 1 for endpoints 4, 5 and 6 ( ping-pong mode) this bit is set by hardware after a new packet has been stored in the endpoint fifo data bank 1 (only in ping-pong mode). then, the endpoint interrupt is triggered if enabled (see ?uepint register uepint (s:f8h read-only) usb endpoint interrupt register? on page 128 ) and all the following out packets to the endpoint bank 1 are rejected (nak?ed) until this bit has been cleared, excepted for isoch ronous endpoints. this bit will be cleared by the device firmware aft er reading the out data from the endpoint fifo. 5 stallrq stall handshake request set this bit to request a stall answer to the host for the next handshake.clear this bit otherwise. for control endpoints: cleared by hardware when a v alid setup pid is received. 4 txrdy tx packet ready set this bit after a packet has been written into t he endpoint fifo for in data transfers. data will b e written into the endpoint fifo only after this bit has been cleared. set this bit without writing data to the endpoint fifo to send a zero length packet. this bit is cleared by hardware, as soon as the pac ket has been sent for isochronous endpoints, or aft er the host has acknowledged the packet for control, bulk and inter rupt endpoints. when this bit is cleared, the endpo int interrupt is triggered if enabled (see ?uepint register uepint (s:f8h read-only) usb endpo int interrupt register? on page 128 ). 3 stlcrc stall sent/crc error flag - for control, bulk and interrupt endpoints: this bit is set by hardware after a stall handshake has been sent as requested by stallrq. then, the e ndpoint interrupt is triggered if enabled (see ?uepint register uepint (s:f8h read-only) usb endpo int interrupt register? on page 128 ) it will be cleared by the device firmware. - for isochronous endpoints (read-only) : this bit is set by hardware if the last received da ta is corrupted (crc error on data). this bit is updated by hardware when a new data is received. 2 rxsetup received setup this bit is set by hardware when a valid setup pack et has been received from the host. then, all the o ther bits of the register are cleared by hardware and the endpoint i nterrupt is triggered if enabled (see ?uepint register uepint (s:f8h read-only) usb endpoint interrupt register? on page 128 ). it will be cleared by the device firmware after rea ding the setup data from the endpoint fifo. 1 rxoutb0 received out data bank 0 (see also rxoutb1 bit for ping-pong endpoints) this bit is set by hardware after a new packet has been stored in the endpoint fifo data bank 0. then, the endpoint interrupt is triggered if enabled (see ?uepint register uepint (s:f8h read-only) usb endpo int interrupt register? on page 128 ) and all the following out packets to the endpoint bank 0 are rejected (nak?ed) until this bit has be en cleared, excepted for isochronous endpoints. however, for co ntrol endpoints, an early setup transaction may ove rwrite the content of the endpoint fifo, even if its data pack et is received while this bit is set. this bit will be cleared by the device firmware aft er reading the out data from the endpoint fifo. 0 txcmpl transmitted in data complete this bit is set by hardware after an in packet has been transmitted for isochronous endpoints and afte r it has been accepted (ack?ed) by the host for control, bulk and interrupt endpoints. then, the endpoint interrupt is triggered if enabled (see ?uepint register uepint (s:f8h read-only) usb endpo int interrupt register? on page 128 ). this bit will be cleared by the device firmware bef ore setting txrdy.
126 7683c?usb?11/07 at83c5134/35/36 table 21-10. uepdatx register uepdatx (s:cfh) usb fifo data endpoint x (x = epnum set in uepnum register uepnum (s:c7h) u sb endpoint number) reset value = xxh table 21-11. ubyctlx register ubyctlx (s:e2h) usb byte count low register x (x = epnum set in uepnum register uepnum (s:c7h) us b endpoint number) reset value = 00h table 21-12. ubycthx register ubycthx (s:e3h) usb byte count high register x (x = epnum set in uepnum register uepnum (s:c7h) us b endpoint number) reset value = 00h 7 6 5 4 3 2 1 0 fdat7 fdat6 fdat5 fdat4 fdat3 fdat2 fdat1 fdat0 bit number bit mnemonic description 7 - 0 fdat [7:0] endpoint x fifo data data byte to be written to fifo or data byte to be read from the fifo, for the endpoint x (see epnum). 7 6 5 4 3 2 1 0 byct7 byct6 byct5 byct4 byct3 byct2 byct1 byct0 bit number bit mnemonic description 7 - 0 byct[7:0] byte count lsb least significant byte of the byte count of a recei ved data packet. the most significant part is provi ded by the ubycthx register ubycthx (s:e3h) usb byte count hig h register x (x = epnum set in uepnum register uepnum (s:c7h) usb endpoint number) (see figure 21- 11 on page 126). this byte count is equal to the number of data bytes received after the data pid. 7 6 5 4 3 2 1 0 - - - - - - byct9 byct8 bit number bit mnemonic description 7-2 - reserved the value read from these bits is always 0. do not set these bits. 2-0 byct[10:8] byte count msb most significant byte of the byte count of a receiv ed data packet. the least significant part is provi ded by ubyctlx register ubyctlx (s:e2h) usb byte count low register x (x = epnum set in uepnum register uepnum (s:c7h) usb endpoint number) (see f igure 21-11 on page 126).
127 7683c?usb?11/07 at83c5134/35/36 table 21-13. ueprst register ueprst (s:d5h) usb endpoint fifo reset register reset value = 00h 7 6 5 4 3 2 1 0 - - ep5rst ep4rst ep3rst ep2rst ep1rst ep0rst bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not se t this bit. 6 - reserved the value read from this bit is always 0. do not se t this bit. 5 ep5rst endpoint 5 fifo reset set this bit and reset the endpoint fifo prior to a ny other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operatio n and start using the fifo. 4 ep4rst endpoint 4 fifo reset set this bit and reset the endpoint fifo prior to a ny other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operatio n and start using the fifo. 3 ep3rst endpoint 3 fifo reset set this bit and reset the endpoint fifo prior to a ny other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operatio n and start using the fifo. 2 ep2rst endpoint 2 fifo reset set this bit and reset the endpoint fifo prior to a ny other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operatio n and start using the fifo. 1 ep1rst endpoint 1 fifo reset set this bit and reset the endpoint fifo prior to a ny other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operatio n and start using the fifo. 0 ep0rst endpoint 0 fifo reset set this bit and reset the endpoint fifo prior to a ny other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operatio n and start using the fifo.
128 7683c?usb?11/07 at83c5134/35/36 table 21-14. uepint register uepint (s:f8h read-only) usb endpoint interrupt register reset value = 00h 7 6 5 4 3 2 1 0 - - ep5int ep4int ep3int ep2int ep1int ep0int bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not se t this bit. 6 - reserved the value read from this bit is always 0. do not se t this bit. 5 ep5int endpoint 5 interrupt this bit is set by hardware when an endpoint interr upt source has been detected on the endpoint 5. the endpoint interrupt sources are in t he uepstax register and can be: txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep5ie bit in the uepien register is set. this bit is cleared by hardware when all the endpoi nt interrupt sources are cleared 4 ep4int endpoint 4 interrupt this bit is set by hardware when an endpoint interr upt source has been detected on the endpoint 4. the endpoint interrupt sources are in t he uepstax register and can be: txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep4ie bit in the uepien register is set. this bit is cleared by hardware when all the endpoi nt interrupt sources are cleared 3 ep3int endpoint 3 interrupt this bit is set by hardware when an endpoint interr upt source has been detected on the endpoint 3. the endpoint interrupt sources are in t he uepstax register and can be: txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep3ie bit in the uepien register is set. this bit is cleared by hardware when all the endpoi nt interrupt sources are cleared 2 ep2int endpoint 2 interrupt this bit is set by hardware when an endpoint interr upt source has been detected on the endpoint 2. the endpoint interrupt sources are in t he uepstax register and can be: txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep2ie bit in the uepien register is set. this bit is cleared by hardware when all the endpoi nt interrupt sources are cleared 1 ep1int endpoint 1 interrupt this bit is set by hardware when an endpoint interr upt source has been detected on the endpoint 1. the endpoint interrupt sources are in t he uepstax register and can be: txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep1ie bit in the uepien register is set. this bit is cleared by hardware when all the endpoi nt interrupt sources are cleared 0 ep0int endpoint 0 interrupt this bit is set by hardware when an endpoint interr upt source has been detected on the endpoint 0. the endpoint interrupt sources are in t he uepstax register and can be: txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep0ie bit in the uepien register is set. this bit is cleared by hardware when all the endpoi nt interrupt sources are cleared
129 7683c?usb?11/07 at83c5134/35/36 table 21-15. uepien register uepien (s:c2h) usb endpoint interrupt enable register reset value = 00h 7 6 5 4 3 2 1 0 - - ep5inte ep4inte ep3inte ep2inte ep1inte ep0inte bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not se t this bit. 6 - reserved the value read from this bit is always 0. do not se t this bit. 5 ep5inte endpoint 5 interrupt enable set this bit to enable the interrupts for this endp oint. clear this bit to disable the interrupts for this e ndpoint. 4 ep4inte endpoint 4 interrupt enable set this bit to enable the interrupts for this endp oint. clear this bit to disable the interrupts for this e ndpoint. 3 ep3inte endpoint 3 interrupt enable set this bit to enable the interrupts for this endp oint. clear this bit to disable the interrupts for this e ndpoint. 2 ep2inte endpoint 2 interrupt enable set this bit to enable the interrupts for this endp oint. clear this bit to disable the interrupts for this e ndpoint. 1 ep1inte endpoint 1 interrupt enable set this bit to enable the interrupts for this endp oint. clear this bit to disable the interrupts for this e ndpoint. 0 ep0inte endpoint 0 interrupt enable set this bit to enable the interrupts for this endp oint. clear this bit to disable the interrupts for this e ndpoint.
130 7683c?usb?11/07 at83c5134/35/36 table 21-16. ufnumh register ufnumh (s:bbh, read-only) usb frame number high register reset value = 00h table 21-17. ufnuml register ufnuml (s:bah, read-only) usb frame number low register reset value = 00h 7 6 5 4 3 2 1 0 - - crcok crcerr - fnum10 fnum9 fnum8 bit number bit mnemonic description 5 crcok frame number crc ok this bit is set by hardware when a new frame number in start of frame packet is received without crc error. this bit is updated after every start of frame pack et receipt. important note: the start of frame interrupt is gen erated just after the pid receipt. 4 crcerr frame number crc error this bit is set by hardware when a corrupted frame number in start of frame packet is received. this bit is updated after every start of frame pack et receipt. important note: the start of frame interrupt is gen erated just after the pid receipt. 3 - reserved the value read from this bit is always 0. do not se t this bit. 2-0 fnum[10:8] frame number fnum[10:8] are the upper 3 bits of the 11-bit frame number (see the ?ufnuml register ufnuml (s:bah, read-only) usb frame number low regi ster? on page 130 ). it is provided in the last received sof packet (see sofin t in the ?usbien register usbien (s:beh) usb global interrupt enable register? on pa ge 122 ). fnum is updated if a corrupted sof is received. 7 6 5 4 3 2 1 0 fnum7 fnum6 fnum5 fnum4 fnum3 fnum2 fnum1 fnum0 bit number bit mnemonic description 7 - 0 fnum[7:0] frame number fnum[7:0] are the lower 8 bits of the 11-bit frame number ( see ?ufnumh register ufnumh (s:bbh, read-only) usb frame number high reg ister? on page 130. ).
131 7683c?usb?11/07 at83c5134/35/36 22. reset 22.1 introduction the reset sources are: power management, hardware w atchdog, pca watchdog and reset input. figure 22-1. reset schematic 22.2 reset input the reset input can be used to force a reset pulse longer than the internal reset controlled by the power monitor. rst input has a pull-up resistor allowing power-on reset by simply connect- ing an external capacitor to v s s as shown in figure 22-2. resistor value and input characteristics are discussed in the section ?dc ch aracteristics? of the at83c5134/35/36 datasheet. figure 22-2. reset circuitry and power-on reset 22.3 reset output as detailed in section ?hardware watchdog timer?, pa ge 138, the wdt generates a 96-clock period pulse on the rst pin. in order to properly p ropagate this pulse to the rest of the applica- tion in case of external capacitor or power-supply supervisor circuit, a 1 k resistor must be added as shown figure 22-3. power monitor hardware watchdog pca watchdog rst internal reset rst rrst vcc to internal reset rst vss + b. power-on reset a. rst input circuitry
132 7683c?usb?11/07 at83c5134/35/36 figure 22-3. recommended reset output schematic rst vss + vss vdd rst 1k to other on-board circuitry at89c5131a-m
133 7683c?usb?11/07 at83c5134/35/36 23. power monitor the por/pfd function monitors the internal power-su pply of the cpu core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. this is achieved by applying an i nternal reset to them. by generating the reset the power monitor insures a correct start up when at89c5131 is pow- ered up. 23.1 description in order to startup and maintain the microcontrolle r in correct operating mode, v cc has to be sta- bilized in the v cc operating range and the oscillator has to be stabi lized with a nominal amplitude compatible with logic level vih/vil. these parameters are controlled during the three ph ases: power-up, normal operation and power going down. see figure 23-1. figure 23-1. power monitor block diagram note: 1. once xtal1 high and low levels reach above a nd below vih/vil. a 1024 clock period delay will extend the reset coming from the power fail de tect. if the power falls below the power fail detect threshold level, the reset will be applied i mmediately. the voltage regulator generates a regulated interna l supply for the cpu core the memories and the peripherals. spikes on the external vcc are smo othed by the voltage regulator. the power fail detect monitor the supply generated by the voltage regulator and generate a reset if this supply falls below a safety threshold as illustrated in the figure 23-2 below. vcc power on reset power fail detect voltage regulator xtal1 (1) cpu core memories peripherals regulated supply rst pin hardware watchdog pca watchdog internal reset
134 7683c?usb?11/07 at83c5134/35/36 figure 23-2. power fail detect when the power is applied, the power monitor immedi ately asserts a reset. once the internal supply after the voltage regulator reach a safety l evel, the power monitor then looks at the xtal clock input. the internal reset will remain asserte d until the xtal1 levels are above and below vih and vil. further more. an internal counter will count 1024 clock periods before the reset is de-asserted. if the internal power supply falls below a safety l evel, a reset is immediately asserted. . vcc t reset vcc
135 7683c?usb?11/07 at83c5134/35/36 24. power management 24.1 idle mode an instruction that sets pcon.0 indicates that it i s the last instruction to be executed before going into the idle mode. in the idle mode, the int ernal clock signal is gated off to the cpu, but not to the interrupt, timer, and serial port functi ons. the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. ale and psen hold at logic high level. there are two ways to terminate the idle mode. acti vation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminating the i dle mode. the interrupt will be serviced, and following reti the next instruction to be execu ted will be the one following the instruction that put the device into idle. the flag bits gf0 and gf1 can be used to give an in dication if an interrupt occurred during nor- mal operation or during an idle. for example, an in struction that activates idle can also set one or both flag bits. when idle is terminated by an in terrupt, the interrupt service routine can exam- ine the flag bits. the other way of terminating the idle mode is with a hardware reset. since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscilla- tor periods) to complete the reset. 24.2 power-down mode to save maximum power, a power-down mode can be inv oked by software (refer to table 13, pcon register). in power-down mode, the oscillator is stopped and t he instruction that invoked power-down mode is the last instruction executed. the internal ram and sfrs retain their value until the power-down mode is terminated. v cc can be lowered to save further power. either a har dware reset or an external interrupt can cause an exit fr om power-down. to properly terminate power- down, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. only: ? external interrupt int0 , ? external interrupt int1 , ? keyboard interrupt and ? usb interrupt are useful to exit from power-down. for that, inter rupt must be enabled and configured as level or edge sensitive interrupt input. when keyboard in terrupt occurs after a power down mode, 1024 clocks are necessary to exit to power-down mod e and enter in operating mode. holding the pin low restarts the oscillator but bri nging the pin high completes the exit as detailed in figure 24-1. when both interrupts are enabled, t he oscillator restarts as soon as one of the two inputs is held low and power-down exit will be completed when the first input is released. in this case, the higher priority interrupt service ro utine is executed. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put at83c5134/35/36 into power-down mode.
136 7683c?usb?11/07 at83c5134/35/36 figure 24-1. power-down exit waveform exit from power-down by reset redefines all the sfr s, exit from power-down by external inter- rupt does no affect the sfrs. exit from power-down by either reset or external in terrupt does not affect the internal ram content. note: if idle mode is activated with power-down mode (idl and pd bits set), the exit sequence is unchanged, when execution is vectored to interrupt, pd and idl bits are cleared and idle mode is not entered. this table shows the state of ports during idle and power-down modes. note: 1. port 0 can force a 0 level. a ?one? will lea ve port floating. int1 int0 xtal power-down phase oscillator restart phase active phase active phase table 24-1. state of ports mode program memory ale psen port0 port1 port2 port3 porti2 idle internal 1 1 port data (1) port data port data port data port data idle external 1 1 floating port data address port data port data power-down internal 0 0 port data (1) port data port data port data port data power-down external 0 0 floating port data port data port data port data
137 7683c?usb?11/07 at83c5134/35/36 24.3 registers table 24-2. pcon register pcon (s:87h) power control register reset value = 10h 7 6 5 4 3 2 1 0 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7 smod1 serial port mode bit 1 set to select double baud rate in mode 1, 2 or 3. 6 smod0 serial port mode bit 0 set to select fe bit in scon register. clear to select sm0 bit in scon register 5 - reserved the value read from this bit is always 0. do not se t this bit. 4 pof power-off flag set by hardware when v cc rises from 0 to its nominal voltage. can also be s et by software. clear to recognize next reset type. 3 gf1 general-purpose flag 1 set by software for general-purpose usage. cleared by software for general-purpose usage. 2 gf0 general-purpose flag 0 set by software for general-purpose usage. cleared by software for general-purpose usage. 1 pd power-down mode bit set this bit to enter in power-down mode. cleared by hardware when reset occurs. 0 idl idle mode bit set this bit to enter in idle mode. cleared by hardware when interrupt or reset occurs.
138 7683c?usb?11/07 at83c5134/35/36 25. hardware watchdog timer the wdt is intended as a recovery method in situati ons where the cpu may be subjected to software upset. the wdt consists of a 14-bit counte r and the watchdog timer reset (wdtrst) sfr. the wdt is by default disabled from e xiting reset. to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when wdt is enabled, it will increment every machine cycle whil e the oscillator is running and there is no way to disable the wdt except through reset (either har dware reset or wdt overflow reset). when wdt overflows, it will drive an output reset low pu lse at the rst -pin. 25.1 using the wdt to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr loca- tion 0a6h. when wdt is enabled, the user needs to s ervice it by writing to 01eh and 0e1h to wdtrst to avoid wdt overflow. the 14-bit counter ov erflows when it reaches 16383 (3fffh) and this will reset the device. when wdt is enabled , it will increment every machine cycle while the oscillator is running. this means the user must reset the wdt at least every 16383 machine cycle. to reset the wdt the user must write 01eh an d 0e1h to wdtrst. wdtrst is a write only register. the wdt counter cannot be read or wr itten. when wdt overflows, it will generate an output reset pulse at the rst -pin. the reset pulse duration is 96 x t clk periph , where t clk periph = 1/f clk periph . to make the best use of the wdt, it should be ser viced in those sec- tions of code that will periodically be executed wi thin the time required to prevent a wdt reset. to have a more powerful wdt, a 2 7 counter has been added to extend the time-out capa bility, ranking from 16 ms to 2s at f osca = 12 mhz. to manage this feature, refer to wdtprg register description, table 25-2. table 25-1. wdtrst register wdtrst - watchdog reset register (0a6h) reset value = xxxx xxxxb write only, this sfr is used to reset/enable the wd t by writing 01eh then 0e1h in sequence. 7 6 5 4 3 2 1 0 - - - - - - - -
139 7683c?usb?11/07 at83c5134/35/36 table 25-2. wdtprg register wdtprg - watchdog timer out register (0a7h) reset value = xxxx x000 25.2 wdt during power-down and idle in power-down mode the oscillator stops, which mean s the wdt also stops. while in power- down mode the user does not need to service the wdt . there are 2 methods of exiting power- down mode: by a hardware reset or via a level activ ated external interrupt which is enabled prior to entering power-down mode. when power-down is exi ted with hardware reset, servicing the wdt should occur as it normally should whenever the at83c5134/35/36 is reset. exiting power-down with an interrupt is significantly diffe rent. the interrupt is held low long enough for the oscillator to stabilize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interru pt pin is held low, the wdt is not started until the interrupt is pulled high. it is suggested that the wdt be reset during the interrupt service routine. to ensure that the wdt does not overflow within a f ew states of exiting of power-down, it is bet- ter to reset the wdt just before entering power-dow n. in the idle mode, the oscillator continues to run. to prevent the wdt from resetting the at83c5134/35/36 while in idle mode, the user should always set up a timer that will periodically exit idle, service the wdt, and re-enter idle mode. 7 6 5 4 3 2 1 0 - - - - - s2 s1 s0 bit number bit mnemonic description 7 - reserved the value read from this bit is undetermined. do no t try to set this bit. 6 - 5 - 4 - 3 - 2 s2 wdt time-out select bit 2 1 s1 wdt time-out select bit 1 0 s0 wdt time-out select bit 0 s2 s1 s0 selected time-out 0 0 0 16384x2^(214 - 1) machine cycles, 16.3 ms at fos c = 12 mhz 0 0 1 16384x2^(215 - 1) machine cycles, 32.7 ms at fos c = 12 mhz 0 1 0 16384x2^(216 - 1) machine cycles, 65.5 ms at fos c = 12 mhz 0 1 1 16384x2^(217 - 1) machine cycles, 131 ms at fosc = 12 mhz 1 0 0 16384x2^(218 - 1) machine cycles, 262 ms at fosc = 12 mhz 1 0 1 16384x2^(219 - 1) machine cycles, 542 ms at fosc = 12 mhz 1 1 0 16384x2^(220 - 1) machine cycles, 1.05 s at fosc = 12 mhz 1 1 1 16384x2^(221 - 1) machine cycles, 2.09 s at fosc = 12 mhz 16384x2^s machine cycles
141 7683b?usb?03/07 at83c5134/35/36 26. reduced emi mode the ale signal is used to demultiplex address and d ata buses on port 0 when used with exter- nal program or data memory. nevertheless, during in ternal code execution, ale signal is still generated. in order to reduce emi, ale signal can b e disabled by setting ao bit. the ao bit is located in auxr register at bit locat ion 0. as soon as ao is set, ale is no longer output but remains active during movx and movc inst ructions and external fetches. during ale disabling, ale pin is weakly pulled high. table 26-1. auxr register auxr - auxiliary register (8eh) reset value = 0x0x 1100b not bit addressable 7 6 5 4 3 2 1 0 dpu - m0 - xrs1 xrs0 extram ao bit number bit mnemonic description 7 dpu disable weak pull up cleared to enabled weak pull up on standard ports set to disable weak pull up on standard ports 6 - reserved the value read from this bit is indeterminate. do n ot set this bit. 5 m0 pulse length cleared to stretch movx control: the rd and the wr pulse length is 6 clock periods (default). set to stretch movx control: the rd and the wr pulse length is 30 clock periods. 4 - reserved the value read from this bit is indeterminate. do n ot set this bit. 3 xrs1 eram size xrs1 xrs0 eram size 0 0 256 bytes 0 1 512 bytes 1 0 768 bytes 1 1 1024 bytes (default) 2 xrs0 1 extram extram bit cleared to access internal eram using movx at ri at dptr. set to access external memory. 0 ao ale output bit cleared, ale is emitted at a constant rate of 1/6 t he oscillator frequency (or 1/3 if x2 mode is used) (default). set , ale is active only during a movx or movc inst ruction is used.
142 7683c?usb?11/07 at83c5134/35/36 27. electrical characteristics 27.1 absolute maximum ratings 27.2 dc parameters t a = -40 c to +85 c; v ss = 0v; v cc = 2.7 - 3.6v; f = 0 to 40 mhz ambient temperature under bias: i = industrial ..................................... ...................-40 c to 85 c storage temperature ................................ .... -65 c to + 150 c voltage on v cc from v ss ......................................-0.5v to + 6v voltage on any pin from v ss .....................-0.5v to v cc + 0.2v note: stresses at or above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other condi - tions above those indicated in the operational sections of this specification is not implied. expo sure to absolute maximum rating conditions may affect device reliability. symbol parameter min typ (5) max unit test conditions v il input low voltage -0.5 0.2vcc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3 and 4 (6) 0.3 0.45 1.0 vv v i ol = 100 a (4) i ol = 0.8 ma (4) i ol = 1.6ma (4) v ol1 output low voltage, port 0, ale, psen (6) 0.3 0.45 1.0 vv v i ol = 200 a (4) i ol = 1.6 ma (4) i ol = 3.5 ma (4) v oh output high voltage, ports 1, 2, 3, 4 and 5 v cc - 0.3 v cc - 0.7 v cc - 1.5 vv v i oh = -10 a i oh = -30 a i oh = -60 a v cc = 2.7 - 3.6v v oh1 output high voltage, port 0, ale, psen v cc - 0.3 v cc - 0.7 v cc - 1.5 vv v i oh = -200 a i oh = -1.6 ma i oh = -3.5 ma v cc = 2.7 - 3.6v r rst rst pullup resistor 50 100 200 k i il logical 0 input current ports 1, 2, 3 and 4 -50 a vin = 0.45v i li input leakage current 10 a 0.45v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3 and 4 -650 a vin = 2.0v c io capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power-down current 100 a 2.7v < v cc < 3.6v (3) i cc power supply current i ccop = 0.33xf(mhz)+1.46 i ccidle = 0.3xf(mhz)+1.46 i ccwrite = 0.8xf(mhz)+15 v cc = 3.3v (1)(2) v pfdp power fail high level threshold 2.7 v
143 7683c?usb?11/07 at83c5134/35/36 notes: 1. operating i cc is measured with all output pins disconnected; xta l1 driven with t clch , t chcl = 5 ns (see figure 27-4.), v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c.; ea = rst = port 0 = v cc . i cc would be slightly higher if a crystal oscillator u sed (see figure 27-1.). 2. idle i cc is measured with all output pins disconnected; xta l1 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c; port 0 = v cc ; ea = rst = v ss (see figure 27-2). 3. power-down i cc is measured with all output pins disconnected; ea = v cc , port 0 = v cc ; xtal2 nc.; rst = v ss (see fig- ure 27-3.). in addition, the wdt must be inactive a nd the pof flag must be set. 4. capacitance loading on ports 0 and 2 may cause sp urious noise pulses to be superimposed on the v ols of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when t hese pins make 1 to 0 transitions during bus operation. in the worst case s (capacitive loading 100 pf), the noise pulse on t he ale line may exceed 0.45v with maxi v ol peak 0.6v. a schmitt trigger use is not necessary. 5. typicals are based on a limited number of samples and are not guaranteed. the values listed are at r oom temperature. 6. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1, 2 and 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. figure 27-1. i cc test condition, active mode v pfdm power fail low level threshold 2.2 v power fail hysteresis v pfdp - v pfdm 0.15 v symbol parameter min typ (5) max unit test conditions ea v cc v cc i cc (nc) clock signal all other pins are disconnected. rst xtal2 xtal1 v ss v cc p0
144 7683c?usb?11/07 at83c5134/35/36 figure 27-2. i cc test condition, idle mode figure 27-3. i cc test condition, power-down mode figure 27-4. clock signal waveform for i cc tests in active and idle modes 27.2.1 led?s note: 1. (t a = -20 c to +50 c, v cc - v ol = 2 v 20%) rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. clock signal v cc rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. v cc v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t clch t chcl t clch = t chcl = 5ns. table 27-1. led outputs dc parameters symbol parameter min typ max unit test conditions i ol output low current, p3.6 and p3.7 led modes 12 5 24 10 48 20 ma ma ma 2 ma configuration 4 ma configuration 10 ma configuration
145 7683c?usb?11/07 at83c5134/35/36 27.3 usb dc parameters 27.4 ac parameters 27.4.1 explanation of the ac symbols each timing symbol has 5 characters. the first char acter is always a ?t? (stands for time). the other characters, depending on their positions, sta nd for the name of a signal or the logical sta- tus of that signal. the following is a list of all the characters and what they stand for. example:t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t a = -40 c to +85 c; v ss = 0v; v cc = 2.7 - 3.6v ; f = 0 to 40 mhz. t a = -40 c to +85 c; v ss = 0v; v cc = 2.7 - 3.6v . (load capacitance for port 0, ale and psen = 60 pf; load capacitance for all other outputs = 60 pf.) table 27-3 , table 27-6 and table 27-9 give the description of each ac symbols. table 27-4 , table 27-8 and table 27-10 give for each range the ac paramete r. table 27-5, table 27-8 and table 27-11 give the frequency derating formula of the ac para me- ter for each speed range description. to calculate each ac symbols. take the x value and use this value in the formula. symbol parameter min typ max unit v ref usb reference voltage 3.0 3.6 v v ih input high voltage for d+ and d- (driven) 2.0 v v ihz input high voltage for d+ and d- (floating) 2.7 3.6 v v il input low voltage for d+ and d- 0.8 v v oh output high voltage for d+ and d- 2.8 3.6 v v ol output low voltage for d+ and d- 0.0 0.3 v 1 4 2 3 1 - v bus 2 - d - 3 - d + 4 - gnd usb ?b? receptacle v ref d + d - r rpad rpad r = 1.5 k r pad = 27
146 7683c?usb?11/07 at83c5134/35/36 example: t lliv and 20 mhz, standard clock. x = 30 ns t = 50 ns t cciv = 4t - x = 170 ns 27.4.2 external program memory characteristics table 27-2. symbol description table 27-3. ac parameters for a fix clock (f = 40 mhz) symbol parameter t oscillator clock period t lhll ale pulse width t avll address valid to ale t llax address hold after ale t lliv ale to valid instruction in t llpl ale to psen t plph psen pulse width t pliv psen to valid instruction in t pxix input instruction hold after psen t pxiz input instruction float after psen t aviv address to valid instruction in t plaz psen low to address float symbol min max units t 25 ns t lhll 40 ns t avll 10 ns t llax 10 ns t lliv 70 ns t llpl 15 ns t plph 55 ns t pliv 35 ns t pxix 0 ns t pxiz 18 ns t aviv 85 ns t plaz 10 ns
147 7683c?usb?11/07 at83c5134/35/36 table 27-4. ac parameters for a variable clock 27.4.3 external program memory read cycle symbol type standard clock x2 clock x parameter units t lhll min 2 t - x t - x 10 ns t avll min t - x 0.5 t - x 15 ns t llax min t - x 0.5 t - x 15 ns t lliv max 4 t - x 2 t - x 30 ns t llpl min t - x 0.5 t - x 10 ns t plph min 3 t - x 1.5 t - x 20 ns t pliv max 3 t - x 1.5 t - x 40 ns t pxix min x x 0 ns t pxiz max t - x 0.5 t - x 7 ns t aviv max 5 t - x 2.5 t - x 40 ns t plaz max x x 10 ns t pliv tplaz ale psen port 0 port 2 a0-a7 a0-a7 instr in instr in instr in address or sfr-p2 address a8-a15 address a8-a15 12 t clcl t aviv t lhll t avll t lliv t llpl t plph t pxav t pxix t pxiz t llax
148 7683c?usb?11/07 at83c5134/35/36 27.4.4 external data memory characteristics table 27-5. symbol description table 27-6. ac parameters for a variable clock (f = 40 mhz) symbol parameter t rlrh rd pulse width t wlwh wr pulse width t rldv rd to valid data in t rhdx data hold after rd t rhdz data float after rd t lldv ale to valid data in t avdv address to valid data in t llwl ale to wr or rd t avwl address to wr or rd t qvwx data valid to wr transition t qvwh data set-up to wr high t whqx data hold after wr t rlaz rd low to address float t whlh rd or wr high to ale high symbol min max units t rlrh 130 ns t wlwh 130 ns t rldv 100 ns t rhdx 0 ns t rhdz 30 ns t lldv 160 ns t avdv 165 ns t llwl 50 100 ns t avwl 75 ns t qvwx 10 ns t qvwh 160 ns t whqx 15 ns t rlaz 0 ns t whlh 10 40 ns
149 7683c?usb?11/07 at83c5134/35/36 table 27-7. ac parameters for a variable clock 27.4.5 external data memory write cycle symbol type standard clock x2 clock x parameter units t rlrh min 6 t - x 3 t - x 20 ns t wlwh min 6 t - x 3 t - x 20 ns t rldv max 5 t - x 2.5 t - x 25 ns t rhdx min x x 0 ns t rhdz max 2 t - x t - x 20 ns t lldv max 8 t - x 4t -x 40 ns t avdv max 9 t - x 4.5 t - x 60 ns t llwl min 3 t - x 1.5 t - x 25 ns t llwl max 3 t + x 1.5 t + x 25 ns t avwl min 4 t - x 2 t - x 25 ns t qvwx min t - x 0.5 t - x 15 ns t qvwh min 7 t - x 3.5 t - x 25 ns t whqx min t - x 0.5 t - x 10 ns t rlaz max x x 0 ns t whlh min t - x 0.5 t - x 15 ns t whlh max t + x 0.5 t + x 15 ns t qvwh t llax ale psen wr port 0 port 2 a0-a7 data out address or sfr-p2 t avwl t llwl t qvwx address a8-a15 or sfr p2 t whqx t whlh t wlwh
150 7683c?usb?11/07 at83c5134/35/36 27.4.6 external data memory read cycle 27.4.7 serial port timing - shift register mode table 27-8. symbol description (f = 40 mhz) table 27-9. ac parameters for a fix clock (f = 40 mhz) table 27-10. ac parameters for a variable clock ale psen rd port 0 port 2 a0-a7 data in address or sfr-p2 t avwl t llwl t rlaz address a8-a15 or sfr p2 t rhdz t whlh t rlrh t lldv t rhdx t llax t avdv symbol parameter t xlxl serial port clock cycle time t qvhx output data set-up to clock rising edge t xhqx output data hold after clock rising edge t xhdx input data hold after clock rising edge t xhdv clock rising edge to input data valid symbol min max units t xlxl 300 ns t qvhx 200 ns t xhqx 30 ns t xhdx 0 ns t xhdv 117 ns symbol type standard clock x2 clock x parameter for -m range units t xlxl min 12 t 6 t ns t qvhx min 10 t - x 5 t - x 50 ns t xhqx min 2 t - x t - x 20 ns t xhdx min x x 0 ns t xhdv max 10 t - x 5 t- x 133 ns
151 7683c?usb?11/07 at83c5134/35/36 27.4.8 shift register timing waveform 27.4.9 external clock drive characteristics (xtal1) table 27-11. ac parameters 27.4.10 external clock drive waveforms 27.4.11 ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic ?1? and 0.45v for a logic ?0?. t iming measurement are made at v ih min for a logic ?1? and v il max for a logic ?0?. 27.4.12 float waveforms for timing purposes as port pin is no longer floati ng when a 100 mv change from load voltage occurs and begins to float when a 100 mv change fro m the loaded v oh /v ol level occurs. i ol /i oh 20 ma. valid valid valid valid valid valid input data valid 0 1 2 3 4 5 6 8 7 ale clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri instruction 0 1 2 3 4 5 6 7 valid symbol parameter min max units t clcl oscillator period 21 ns t chcx high time 5 ns t clcx low time 5 ns t clch rise time 5 ns t chcl fall time 5 ns t chcx /t clcx cyclic ratio in x2 mode 40 60 % v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t chcl t clcx t clcl t clch t chcx input/output 0.2 v cc + 0.9 0.2 v cc - 0.1 v cc -0.5v 0.45v float v oh - 0.1 v v ol + 0.1 v v load v load + 0.1 v v load - 0.1 v
152 7683c?usb?11/07 at83c5134/35/36 27.4.13 clock waveforms valid in normal clock mode. in x2 mode xtal2 must b e changed to xtal2/2. this diagram indicates when signals are clocked int ernally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperature and pin loading. propa- gation also varies from output to output and compon ent. typically though (t a = 25 c fully loaded) rd and wr propagation delays are approximately 50 ns. the other signals a re typically 85 ns. propagation delays are incorpor ated in the ac specifications. data pcl out data pcl out data pcl out sampled sampled sampled state4 state5 state6 state1 state2 state3 state4 state5 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 float float float these signals are not activated during the execution of a movx instruction indicates address transitions external program memory fetch float data sampled dpl or rt out indicates dph or p2 sfr to pch transition pcl out (if program memory is external) pcl out (even if program memory is internal) pcl out (if program memory is external) old data new data p0 pins sampled p1, p2, p3 pins sampled p1, p2, p3 pins sampled p0 pins sampled rxd sampled internal clock xtal2 ale psen p0 p2 (ext) read cycle write cycle rd p0 p2 wr port operation mov port src mov dest p0 mov dest port (p1. p2. p3) (includes into. int1. to t1) serial port shift clock txd (mode 0) data out dpl or rt out indicates dph or p2 sfr to pch transition p0 p2 rxd sampled
153 7683c?usb?11/07 at83c5134/35/36 table 27-12. memory ac timing vdd = 3.3v 10%, t a = -40 to +85 c 27.5 usb ac parameters 27.6 spi interface ac parameters 27.6.0.1 definition of symbols table 27-14. spi interface timing symbol definitions symbol parameter min typ max unit t svrl input psen valid to rst edge 50 ns t rlsx input psen hold after rst edge 50 ns rise time fall time v crs differential data lines 90% 10% 90% 10% t r t f v hmin v lmax table 27-13. usb ac parameters symbol parameter min typ max unit test conditions t r rise time 4 20 ns t f fall time 4 20 ns t fdrate full-speed data rate 11.9700 12.0300 mb/s v crs crossover voltage 1.3 2.0 v t dj1 source jitter total to next transaction -3.5 3.5 ns t dj2 source jitter total for paired transactions -4 4 ns t jr1 receiver jitter to next transaction -18.5 18.5 ns t jr2 receiver jitter for paired transactions -9 9 ns signals conditions c clock h high i data in l low o data out v valid x no longer valid z floating
154 7683c?usb?11/07 at83c5134/35/36 27.6.0.2 timings test conditions: capacitive load on all pins= 50 pf . table 27-15. spi interface master ac timing v dd = 2.7 to 5.5 v, t a = -40 to +85 c note: t per is xtal period when spi interface operates in x2 m ode or twice xtal period when spi interface operates in x1 mode. symbol parameter min max unit slave mode t chch clock period 2 t per t chcx clock high time 0.8 t per t clcx clock low time 0.8 t per t slch , t slcl ss low to clock edge 100 ns t ivcl , t ivch input data valid to clock edge 50 ns t clix , t chix input data hold after clock edge 50 ns t clov, t chov output data valid after clock edge 50 ns t clox , t chox output data hold time after clock edge 0 ns t clsh , t chsh ss high after clock edge 0 ns t slov ss low to output data valid 4t per +20 ns t shox output data hold after ss high 2t per +100 ns t shsl ss high to ss low 2t per +120 t ilih input rise time 2 s t ihil input fall time 2 s t oloh output rise time 100 ns t ohol output fall time 100 ns master mode t chch clock period 4 t per t chcx clock high time 2t per -20 ns t clcx clock low time 2t per -20 ns t ivcl , t ivch input data valid to clock edge 50 ns t clix , t chix input data hold after clock edge 50 ns t clov, t chov output data valid after clock edge 20 ns t clox , t chox output data hold time after clock edge 0 ns
155 7683c?usb?11/07 at83c5134/35/36 27.6.0.3 waveforms figure 27-5. spi slave waveforms (cpha= 0) note: 1. not defined but generally the msb of the cha racter which has just been received. figure 27-6. spi slave waveforms (cpha= 1) note: 1. not defined but generally the lsb of the cha racter which has just been received. t slcl t slch t chcl t clch mosi (input) sck (cpol= 0) (input) ss (input) sck (cpol= 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov (1) t shox t shsl t chsh t clsh t chcl t clch mosi (input) sck (cpol= 0) (input) ss (input) sck (cpol= 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t clov t chov t clox t chox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov (1) t shox t shsl t chsh t clsh t slcl t slch
156 7683c?usb?11/07 at83c5134/35/36 figure 27-7. spi master waveforms (sscpha= 0) note: 1. ss handled by software using general purpose port pin . figure 27-8. spi master waveforms (sscpha= 1) ss handled by software using general purpose port pin . mosi (input) sck (cpol= 0) (output) ss (output) sck (cpol= 1) (output) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch mosi (input) sck (cpol= 0) (output) ss (1) (output) sck (cpol= 1) (output) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch
157 7683c?usb?11/07 at83c5134/35/36 28. ordering information table possible order entries part number memory size supply voltage temperature ran ge package packing at83c5134xxx-pntul 8kb 2.7 to 3.6v industrial & green q fn32 tray at83c5135xxx-pntul 16kb 2.7 to 3.6v industrial & green qfn32 tray at83c5136xxx-pntul 32kb 2.7 to 3.6v industrial & green qfn32 tray at83c5136xxx-pltul 32kb 2.7 to 3.6v industrial & green qfn/mlf48 tray at83c5136xxx-tisul 32kb 2.7 to 3.6v industrial & green so28 stick at83c5136-rdtul 32 2.7 to 3.6v industrial & green vqfp6 4 tray at83c5136xxx-ddw 32kb 2.7 to 3.6v industrial & green di e inked wafer at83ec5136xxx-pntul 32kb with 512-byte of eeprom 2.7 to 3.6v industrial & green qfn/mlf48 tray at83ei5136xxx-pntul 32kb with 32-kbyte of eeprom 2.7 to 3.6v industrial & green qfn/mlf48 tray
158 7683c?usb?11/07 at83c5134/35/36 29. packaging information 29.1 64-lead vqfp
159 7683c?usb?11/07 at83c5134/35/36 29.2 48-lead mlf
160 7683c?usb?11/07 at83c5134/35/36
161 7683c?usb?11/07 at83c5134/35/36 29.3 28-lead so
162 7683c?usb?11/07 at83c5134/35/36 29.4 qfn32
163 7683c?usb?11/07 at83c5134/35/36 30. document revision history 30.1 changes from rev a. to rev. b 1. added qfn32 package. 30.2 changes from rev b. to rev. c 1. updated package drawings.
164 7683c?usb?11/07 at83c5134/35/36 1 features .......................................... ................................................... ....... 1 2 description ....................................... ................................................... ..... 1 3 block diagram ..................................... ................................................... .. 3 4 pinout description ................................ ................................................... 4 4.1 pinout .......................................... ................................................... ................... 4 4.2 signals......................................... ................................................... ................... 6 5 typical application ............................... ................................................. 1 1 5.1 recommended external components ................. ............................................ 11 5.2 pcb recommandations ............................. ................................................... .. 12 6 clock controller .................................. ................................................... 13 6.1 introduction.................................... ................................................... ............... 13 6.2 oscillator...................................... ................................................... ................. 13 6.3 pll ............................................. ................................................... .................. 14 6.4 registers ....................................... ................................................... ............... 16 7 sfr mapping ....................................... ................................................... 18 8 program/code memory ............................... .......................................... 25 8.1 external code memory access ..................... .................................................. 25 9 at89c5131 rom ..................................... ............................................... 27 9.1 rom structure................................... ................................................... ........... 27 9.2 rom lock system................................. ................................................... ....... 27 10 stacked eeprom................................... ................................................ 29 10.1 overview....................................... ................................................... ................ 29 10.2 protocol ....................................... ................................................... ................. 29 11 on-chip expanded ram (eram) ...................... .................................... 30 12 timer 2 .......................................... ................................................... ....... 33 12.1 auto-reload mode ............................... ................................................... .......... 33 12.2 programmable clock output ...................... ................................................... .. 34 13 programmable counter array (pca)................. ................................... 38 13.1 pca capture mode ............................... ................................................... ....... 45 13.2 16-bit software timer/compare mode ............. ............................................... 45 13.3 high speed output mode ......................... ................................................... .... 46 13.4 pulse width modulator mode ..................... ................................................... .. 47
165 7683c?usb?11/07 at83c5134/35/36 13.5 pca watchdog timer............................. ................................................... ...... 48 14 serial i/o port .................................. ................................................... .... 49 14.1 framing error detection ........................ ................................................... ....... 49 14.2 automatic address recognition .................. ................................................... . 50 14.3 baud rate selection for uart for mode 1 and 3.. .......................................... 52 14.4 uart registers................................. ................................................... ........... 55 15 dual data pointer register....................... ............................................. 59 16 interrupt system ................................. ................................................... 61 16.1 overview....................................... ................................................... ................ 61 16.2 registers ...................................... ................................................... ................ 62 16.3 interrupt sources and vector addresses......... ................................................ 69 17 keyboard interface ............................... ................................................. 7 0 17.1 introduction................................... ................................................... ................ 70 17.2 description.................................... ................................................... ................ 70 17.3 registers ...................................... ................................................... ................ 71 18 programmable led................................. ............................................... 74 19 serial peripheral interface (spi) ................ ........................................... 75 19.1 features ....................................... ................................................... ................ 75 19.2 signal description............................. ................................................... ............ 75 19.3 functional description ......................... ................................................... ......... 77 20 two wire interface (twi) ......................... .............................................. 84 20.1 description.................................... ................................................... ................ 86 20.2 notes .......................................... ................................................... .................. 89 20.3 registers ...................................... ................................................... ................ 99 21 usb controller ................................... .................................................. 101 21.1 description.................................... ................................................... .............. 101 21.2 configuration .................................. ................................................... ............ 103 21.3 read/write data fifo........................... ................................................... ..... 105 21.4 bulk/interrupt transactions.................... ................................................... ..... 106 21.5 control transactions ........................... ................................................... ....... 111 21.6 isochronous transactions ....................... ................................................... ... 112 21.7 miscellaneous.................................. ................................................... ........... 113 21.8 suspend/resume management ...................... .............................................. 114
166 7683c?usb?11/07 at83c5134/35/36 21.9 detach simulation .............................. ................................................... ........ 117 21.10 usb interrupt system.......................... ................................................... ....... 117 21.11 usb registers ................................. ................................................... ........... 120 22 reset ............................................ ................................................... ...... 131 22.1 introduction................................... ................................................... .............. 131 22.2 reset input .................................... ................................................... ............. 131 22.3 reset output ................................... ................................................... ........... 131 23 power monitor .................................... .................................................. 133 23.1 description.................................... ................................................... .............. 133 24 power management ................................. ............................................ 135 24.1 idle mode...................................... ................................................... .............. 135 24.2 power-down mode................................ ................................................... ...... 135 24.3 registers ...................................... ................................................... .............. 137 25 hardware watchdog timer .......................... ....................................... 138 25.1 using the wdt .................................. ................................................... ......... 138 25.2 wdt during power-down and idle ................. ............................................... 139 26 reduced emi mode ................................. ............................................. 141 27 electrical characteristics ....................... ............................................. 142 27.1 absolute maximum ratings ...................... ................................................... . 142 27.2 dc parameters.................................. ................................................... ......... 142 27.3 usb dc parameters .............................. ................................................... .... 145 27.4 ac parameters .................................. ................................................... ......... 145 27.5 usb ac parameters.............................. ................................................... ..... 153 27.6 spi interface ac parameters .................... ................................................... . 153 28 ordering information ............................. .............................................. 157 29 packaging information ............................ ............................................ 158 29.1 64-lead vqfp................................... ................................................... .......... 158 29.2 48-lead mlf .................................... ................................................... ........... 159 29.3 28-lead so ..................................... ................................................... ............ 161 29.4 qfn32 .......................................... ................................................... .............. 162 30 document revision history ........................ ........................................ 163 30.1 changes from rev a. to rev. b .................. .................................................. 163 30.2 changes from rev b. to rev. c .................. .................................................. 163
7683c?usb?11/07 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support enter product line e-mail sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in co nnection with atmel products. no license, express o r implied, by estoppel or otherwise, to any intellectual property right is granted by this docum ent or in connection with the sale of atmel product s. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel as sumes no liability whatsoever and disclaims any exp ress, implied or statutory warranty relating to its products including, but no t limited to, the implied warranty of merchantabili ty, fitness for a particular purpose, or non-infringement. in no event shall atm el be liable for any direct, indirect, consequentia l, punitive, special or inciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or los s of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of suc h damages. atmel makes no representations or warranties with respect to the ac curacy or completeness of the contents of this docu ment and reserves the right to make changes to spec ifications and product descriptions at any time without notice . atmel does not make any commitment to update the information contained herein. unless specifically p rovided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atm el?s products are not intended, authorized, or warr anted for use as components in applications intended to support o r sustain life. ? 2007 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others are reg istered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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